A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes an oxide over a substrate; a first conductor and a second conductor being over the oxide and isolated from each other; a third conductor in contact with a top surface of the first conductor; a fourth conductor in contact with a tops surface of the second conductor; a first insulator being over the third conductor and the fourth conductor and having an opening; a second insulator that is positioned in the opening in the first insulator and in contact with the top surface of the first conductor, the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator over the second insulator; and a fifth conductor over the third insulator. The opening in the first insulator overlaps with a region between the third conductor and the fourth conductor. The third insulator is in contact with a top surface of the oxide in a region between the first conductor and the second conductor. A distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor in a cross-sectional view of a transistor in the channel length direction.

A semiconductor device includes a first gate-all-around field-effect transistor (GAA FET) device including a first gate stack having first channels and dielectric material including first and second portions having respective thicknesses formed around the first interfacial layers. The semiconductor device further includes a second GAA FET device including a second gate stack having second channels and the dielectric material formed around the second interfacial layers. A threshold voltage (Vt) shift associated with the semiconductor device is achieved based on a thickness of the first portion of the dielectric material.

A semiconductor device according to an embodiment of the present invention includes: a first oxide insulating layer; an oxide semiconductor layer above the first oxide insulating layer; a second oxide insulating layer covering the oxide semiconductor layer; a nitride insulating layer above the second oxide insulating layer; a gate electrode above the nitride insulating layer; and an insulating layer covering the gate electrode, wherein the nitride insulating layer has a first sidewall having a shape matching a pattern of the gate electrode in a plan view, and the first sidewall is in contact with the insulating layer.

A transistor and a display device including the same are discussed. The transistor can include an active layer, a gate electrode having a region overlapping with the active layer, a gate insulating layer disposed between the active layer and the gate electrode, and a plurality of holes in the gate insulating layer at an outside of the overlap area between the gate electrode and the active layer.

A transistor and a display apparatus including the transistor are discussed. The transistor can include a substrate, a gate electrode disposed on the substrate, a first insulating layer disposed on the gate electrode, and a semiconductor layer disposed on the first insulating layer so as to overlap the gate electrode in a vertical direction. An upper surface of the first insulating layer includes at least one step.

A semiconductor device (200) includes an oxide (230) over a substrate: a first conductor (242a1) and a second conductor (242b1) that are over the oxide and separated from each other; a third conductor (242a2) in contact with a part of a top surface of the first conductor; a fourth conductor (242b2) in contact with a part of a top surface of the second conductor; a first insulator (271a, 271b) that is positioned over the third conductor and the fourth conductor and has an opening overlapping with a region between the third conductor and the fourth conductor; a second insulator (255) that is positioned in the opening of the first insulator and in contact with another part of the top surface of the first conductor, another part of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator (250) that is positioned in the opening of the first insulator and in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second conductor; and a fifth conductor that is positioned over the third insulator in the opening of the first insulator and includes a region overlapping with the oxide with the third insulator therebetween. A distance (L2) between the first conductor and the second conductor is smaller than a distance (L1) between the third conductor and the fourth conductor.

A semiconductor structure includes a first nanosheet channel layer having a first middle portion and first outer portions, a second nanosheet channel layer disposed over the first nanosheet channel layer, the second nanosheet channel layer having a second middle portion and second outer portions, wherein a first distance between the first middle portion and the second middle portion defines a first region and a second distance between the first outer portions and the second outer portions defines a second region, wherein the second distance is less than the first distance, a gate dielectric layer disposed in the first region and the second region, wherein the gate dielectric layer pinches off the second region, and a conductive gate layer disposed on the gate dielectric layer disposed in the first region.

The present disclosure relates to a thin film transistor and a method of manufacturing a thin film transistor. The thin film transistor includes: a substrate; an insulation layer on an upper surface of the substrate; a fin gate on an upper surface of the insulation layer; a surrounding gate dielectric layer and a surrounding channel, where the surrounding gate dielectric layer covers a top surface of the fin gate and a side surface of the fin gate, and the surrounding channel surrounds an outer wall of the surrounding gate dielectric layer; and a source region and a drain region on the upper surface of the substrate, where the source region and the drain region are located on two opposite sides of the fin gate respectively and are in contact with the surrounding channel.

A display device includes a TFT layer having a stack of, in sequence, a first inorganic insulating film composed of a first inorganic material, a second inorganic insulating film composed of a second inorganic material different from the first inorganic material, a first metal film composed of a metal material containing molybdenum a principal component, an oxide semiconductor film composed of an oxide semiconductor, a gate insulating film, and a second metal film. The second inorganic insulating film is provided between the first inorganic insulating film and a first electrode formed from the first metal film, and between the first inorganic insulating film and a second electrode formed from the first metal film.

An oxide semiconductor film with high carrier mobility is provided. The oxide semiconductor film contains indium and oxygen. The oxide semiconductor film includes a crystal grain. The gallium concentration and the zinc concentration in the oxide semiconductor film are each lower than or equal to 0.1 atomic %. The extension length of a grain boundary in the oxide semiconductor film is greater than or equal to 0 nm and less than or equal to 10000 nm. The extension length of the grain boundary is calculated using a field of view of 90 nm square extracted from a TEM image of the oxide semiconductor film. The oxide semiconductor film has a property of transmitting oxygen in a range higher than or equal to 210.sup.20 atoms/cm.sup.3 and lower than or equal to 110.sup.21 atoms/cm.sup.3 in heat treatment at a heating temperature of 400 C. for a treatment time of 8 hours.