A thin film transistor includes a substrate. A first electrode is disposed on the substrate. The first electrode has a first opening defined therein. A first insulating layer is disposed on the first electrode. The first insulating layer has a second opening defined therein. The second opening overlaps the first opening. A second electrode is disposed on the first insulating layer and has a third opening defined therein. The third opening overlaps the first opening. A semiconductor layer is disposed on the second electrode and overlaps the first opening, the second opening, and the third opening. A second insulating layer is disposed on the semiconductor layer. A gate electrode is disposed on the second insulating layer.

A method of forming a semiconductor device includes: forming, in a first device region of the semiconductor device, first nanostructures over a first fin that protrudes above a substrate; forming, in a second device region of the semiconductor device, second nanostructures over a second fin that protrudes above the substrate, where the first and the second nanostructures include a semiconductor material and extend parallel to an upper surface of the substrate; forming a dielectric material around the first and the second nanostructures; forming a first hard mask layer in the first device region around the first nanostructures and in the second device region around the second nanostructures; removing the first hard mask layer from the second device region after forming the first hard mask layer; and after removing the first hard mask layer, increasing a first thickness of the dielectric material around the second nanostructures by performing an oxidization process.

An integrated circuit includes a plurality of stacked channels, a hard mask structure above the channels, and a gate metal above the hard mask structure and wrapped around the channels. The integrated circuit includes a high-K gate dielectric layer wrapped around the channels, wherein a top of the hard mask structure is higher than a top of the high-K gate dielectric layer.

A thin-film transistor includes a substrate; a first electrode on the substrate; a first gate electrode on the first electrode; a first buffer layer between the first electrode and the first gate electrode; a first gate insulating layer on the first gate electrode; a second electrode on the first gate insulating layer; an active layer being extended in a horizontal direction along a bottom surface and in a normal direction along an internal wall of a first opening penetrating the first gate electrode, the first buffer layer, the first gate insulating layer, and the second electrode, and connected to the first electrode and the second electrode; a second gate electrode being extended along a surface of the active layer; and a second gate insulating layer between the active layer and the second gate electrode.

Disclosed in the present disclosure are a transistor device and a memory. The transistor device comprises: a gate; a semiconductor channel, which surrounds a surface of the gate, wherein the semiconductor channel comprises a multi-layer thin film structure, and the multi-layer thin film structure comprises an indium oxide thin film layer, a gallium oxide thin film layer and a zinc oxide thin film layer; a first source drain, which is disposed at a first end of the semiconductor channel; and a second source drain, which is disposed at a second end of the semiconductor channel. By means of the present disclosure, the control ability of the turn-off of the semiconductor channel and the mobility of the semiconductor channel can be adjusted and balanced.

A semiconductor device including a transistor, the transistor includes a first gate electrode, a first gate insulating film provided on the first gate electrode, an oxide semiconductor layer provided on the first gate insulating film, overlapping the first gate electrode, and having a polycrystalline structure, a second gate insulating film provided on the oxide semiconductor layer, and a second gate electrode provided on the second gate insulating film and overlapping the first gate electrode, wherein the first gate electrode has a first region and a second region, the first region overlaps the oxide semiconductor layer and protrudes in a first direction from the second gate electrode in a plan view, and the second region overlaps the second gate electrode and protrudes in a second direction that intersects the first direction from the oxide semiconductor layer in a plan view.

A semiconductor device may include a substrate insulating layer, a semiconductor pattern extending on the lower insulating pattern, a plurality of channel layers stacked on the semiconductor pattern, a gate structure surrounding the plurality of channel layers, a source/drain region on the semiconductor pattern and opposite sides of the gate structure, a backside contact structure including a contact region connected to the source/drain region, and an intermediate insulating pattern in contact with the semiconductor pattern. The backside contact structure may include a metal-semiconductor compound layer, a first insulating liner layer, a second insulating liner layer, and a conductive layer. The backside contact structure may pass through each of the substrate insulating layer, and the semiconductor pattern. The conductive layer may have a step portion between a first vertical region and a second vertical region of the backside contact structure.

A transistor having a minute size is provided. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, a second insulating layer, and a semiconductor layer. The first insulating layer is provided over the first conductive layer and includes an opening reaching the first conductive layer and a depressed portion surrounding the opening in a plan view. The second conductive layer is provided to cover the inner wall of the depressed portion and includes a region facing the semiconductor layer with the first insulating layer therebetween. The semiconductor layer is provided to include a region overlapping with the opening and is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the top surface of the second conductive layer. The second insulating layer is provided in contact with the top surface of the semiconductor layer. The third conductive layer is provided over the second insulating layer to cover the inner wall of the opening and includes a region facing the semiconductor layer with the second insulating layer therebetween.

A semiconductor device includes: a word line stack disposed over a lower structure and including a plurality of word lines stacked in a direction vertical to a surface of the lower structure; and pillar-shaped slits penetrating edge parts of the word lines and including an etch stopper.

The disclosure provides a display panel and a display device. The display panel includes an active layer, a first gate insulating layer, a first gate, and a second gate insulating layer; the first gate insulating layer covers the active layer; the first gate is disposed on a side of the first gate insulating layer away from the active layer; the second gate insulating layer is disposed on a side of the first gate insulating layer away from the active layer and covers the first gate, and the second gate insulating layer contains hydrogen element; and the first gate insulating layer includes a first sub-portion disposed between the active layer and the first gate, and a second sub-portion connected to the first sub-portion, and a thickness of the first sub-portion is greater than a thickness of the second sub-portion.