A method of manufacturing a semiconductor device includes forming a pair of source/drain patterns on a substrate, exposing a plurality of semiconductor patterns between the pair of source/drain patterns, forming a gate insulating layer on the exposed plurality of semiconductor patterns, and forming a gate electrode on the gate insulating layer, where the gate insulating layer includes an inner gate insulating layer adjacent to an inner electrode of the gate electrode, and an outer gate insulating layer adjacent to an outer electrode of the gate electrode.

A semiconductor device that occupies a small area is provided. The semiconductor device includes a first insulating layer, a second insulating layer, and a transistor. The transistor includes a semiconductor layer, a gate insulating layer, a gate electrode, a source electrode, and a drain electrode. The source electrode and the drain electrode are provided over the first insulating layer. The second insulating layer includes an opening reaching the first insulating layer and overlapping with part of the source electrode and part of the drain electrode. The semiconductor layer is provided in contact with a side surface of the second insulating layer in the opening, a top surface of the first insulating layer in the opening, a top surface of the source electrode, and a top surface of the drain electrode. The gate insulating layer is positioned over the semiconductor layer, the source electrode, and the drain electrode. The gate electrode overlaps with the opening and is positioned over the gate insulating layer.

An embodiment of the present disclosure provides a thin film transistor including an active layer, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, and a capping layer on the gate insulating layer, wherein the gate electrode and the capping layer are spaced apart from each other, wherein a part of the active layer overlaps the gate electrode, and wherein another part of the active layer overlaps the capping layer, and provides a method for manufacturing a thin film transistor and display device including the same.

A semiconductor device comprises an oxide semiconductor layer having a polycrystalline structure on an insulating surface; a first gate insulating layer on the semiconductor oxide layer; an intermediate layer on the first gate insulating layer; a second gate insulating layer on the intermediate layer; and a gate wiring on the second gate insulating layer. The oxide semiconductor layer has a channel region and a conductive region. The first gate insulating layer overlaps the channel region and the conductive region. The second gate insulating layer overlaps the channel region and does not overlap the conductive region. A sheet resistance of the third region is less than 1000 ohm/square.

A semiconductor device is provided over a base insulating layer including hydrogen. A first conductive layer, a spacer, and a second conductive layer are provided over the base insulating layer. The spacer and the second conductive layer comprise an opening reaching the first conductive layer in which a metal oxide layer is provided. The metal oxide layer includes a region in contact with the first conductive layer and the second conductive layer. The first conductive layer and the second conductive layer function as one and the other of a source electrode and a drain electrode of the transistor. A gate insulating layer is provided over the metal oxide layer to include a region positioned in the opening. A gate electrode is provided to include a region facing the metal oxide layer with the gate insulating layer between the region and the metal oxide layer in the opening.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having nanoribbons selectively removed to allow for thicker gate dielectric materials. In forming an alternating stack of semiconductor and sacrificial layers, a cladding layer is applied to those semiconductor layers to be removed during nanoribbon release. Prior to nanoribbon release, atoms of the cladding layer are diffused into only those semiconductor layers having the cladding. During nanoribbon release etch, the sacrificial layers and those semiconductor layers having diffused atoms therein are removed while the semiconductor layers without cladding remain. By removing nanoribbons, an increased ribbon-to-ribbon spacing is attained for application of thicker gate dielectric materials in gate all around field effect transistors.

Techniques are provided to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine and nanosheets with a wrapped-around gate dielectric. The dielectric spine may be formed prior to the formation of gate structures. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction centrally aligned between the first and second semiconductor regions. The gate dielectric of the gate structures on either side of the dielectric spine is wrapped around the semiconductor regions, such that the gate dielectric is present between the nanosheets and the dielectric spine along the second direction. The dielectric spine may include a dielectric liner that itself is removed prior to formation of the gate structures, thus provided space for the wrapped-around gate dielectric.

In an embodiment, a method of forming a semiconductor device is described that includes forming an opening to a stack of nanostructures, wherein sidewalls of the opening are provided by a gate spacer and an inner spacer. The method may further include applying an oxidizing plasma to the stack of nanostructures in the opening and the surfaces of the gate spacer and the inner spacer providing the sidewalls for the opening. In some embodiments, the oxidizing plasma forms a uniform thickness oxide surface on the stack of nanostructures in the opening and the surfaces of the gate spacer and the inner spacer. The method may further includes forming a high-k gate dielectric on the uniform thickness oxide surface on the stack of nanostructures in the opening and the surfaces of the gate spacer and the inner spacer, and forming a gate electrode on the high-k gate dielectric.

A semiconductor device that can be reduced in size or highly integrated is provided. The semiconductor device includes first and second transistors and first to third conductors. The first transistor includes first and second gate electrodes between which a semiconductor layer of the first transistor is positioned. The second gate electrode is provided over the semiconductor layer of the first transistor to overlap the first gate electrode. The second transistor includes a third gate electrode over a semiconductor layer of the second transistor. The second transistor is stacked over the first transistor. The third gate electrode overlaps the second gate electrode. The first conductor electrically connects a source electrode of the first transistor and a source electrode of the second transistor. The second conductor electrically connects a drain electrode of the first transistor and a drain electrode of the second transistor. The third conductor electrically connects the first gate electrode, the second gate electrode, and the third gate electrode.

A method for forming a semiconductor structure includes alternately forming a plurality of channel layers and a plurality of sacrificial layers over a substrate. The method includes forming a top sacrificial layer over the channel layers and the sacrificial layers. The method includes forming a source/drain trench through the top sacrificial layer, the channel layers, and the sacrificial layers. The method includes recessing the top sacrificial layer and the sacrificial layers through the source/drain trench so that a first width of the top sacrificial layer is less than a second width of the sacrificial layers. The method includes forming a plurality of inner spacers on sidewalls of the top sacrificial layer and sidewalls of the sacrificial layers. The method includes replacing the top sacrificial layer and the sacrificial layers with a gate structure.