According to one embodiment, a semiconductor device includes an insulating substrate, a first semiconductor layer formed of silicon and positioned above the insulating substrate, a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer, a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer, and a block layer positioned between the first semiconductor film and the second semiconductor layer, the block layer hydrogen diffusion of which is lower than that of the first insulating film.

The manufacturing method of the thin film transistor includes the following steps. A gate, a first insulating layer, a second insulating layer, a metal oxide semiconductor layer, a first etching stop layer, a second etching stop layer and a photoresist structure are sequentially formed. The second etching stop layer, the first etching stop layer, and the metal oxide semiconductor layer are patterned using the photoresist structure as a mask to form a pre-second etching stop pattern, a pre-first etching stop pattern, and a metal oxide semiconductor pattern. The pre-second etching stop pattern and the pre-first etching stop pattern are patterned using the remaining thick portion of the photoresist structure as a mask to form a second etching stop pattern and a first etching stop pattern, and a portion of the second insulating layer is removed to form an insulating pattern. A source and a drain are formed.

A transistor with stable electrical characteristics is provided. The transistor includes a first insulator over a substrate; first to third oxide insulators over the first insulator; a second insulator over the third oxide insulator; a first conductor over the second insulator; and a third insulator over the first conductor. An energy level of a conduction band minimum of each of the first and second oxide insulators is closer to a vacuum level than that of the oxide semiconductor is. An energy level of a conduction band minimum of the third oxide insulator is closer to the vacuum level than that of the second oxide insulator is. The first insulator contains oxygen. The number of oxygen molecules released from the first insulator measured by thermal desorption spectroscopy is greater than or equal to 1E14 molecules/cm.sup.2 and less than or equal to 1E16 molecules/cm.sup.2.

A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.

A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a second source/drain of a second transistor on the substrate adjacent to the first source/drain, an isolation region arranged in the substrate between the first source/drain and the second source/drain; depositing a spacer material on the first source/drain; depositing the spacer material on the second source/drain; forming a first channel extending from the first source drain and through the spacer material; forming a second channel extending from the second source/drain and through the spacer material; wherein the spacer material on the first source/drain forms a first spacer and the spacer material on the second source/drain forms a second spacer, the first spacer being different in thickness than the second spacer.

A method of manufacturing a thin-film transistor includes forming an oxide semiconductor on a substrate, stacking an insulating layer and a metal layer on the substrate to cover the oxide semiconductor, forming a photosensitive pattern on the metal layer, forming a gate electrode by etching the metal layer using the photosensitive pattern as a mask, where a part of the gate electrode overlaps a first oxide semiconductor region of the oxide semiconductor, forming a gate insulating film by partially etching the insulating layer using the photosensitive pattern as a mask, where the gate insulating film includes a first insulating region with a first thickness under the photosensitive pattern and a second insulating region with a second thickness less than the first thickness, and performing plasma processing on the gate insulating film so that a second oxide semiconductor region of the oxide semiconductor under the second insulating region becomes conductive.

The present invention provides a field effect transistor and the method for preparing such a filed effect transistor. The filed effect transistor comprises a semiconductor, germanium nanowires, a first III-V compound layer surrounding the germanium nanowires, a semiconductor barrier layer, a gate dielectric layer and a gate electrode sequentially formed surrounding the first III-V compound layer, and source/drain electrodes are respectively located at each side of the gate electrode and on the first III-V compound layer. According to the present invention, the band width of the barrier layer is greater than that of the first III-V compound layer, and the band curvatures of the barrier layer and the first III-V compound layer are different, therefore, a two-dimensional electron gas (2DEG) is formed in the first III-V compound layer near the barrier layer boundary. Since the 2DEG has higher mobility, the performance of the filed effect transistor improved. Besides, the performance of the filed effect transistor also improved due to the structure is a gate-all-around structure.

A semiconductor structure formed based on a buried oxide (BOX) layer configured as a gate dielectric; a substrate adjacent to the BOX layer configured as a first gate electrode; a first source structure and a first drain structure, each residing above the BOX layer; a first channel structure residing between the first drain and first source structures; a second gate electrode residing above the first channel structure; a first shallow trench isolation (STI) structure and a second STI structure, each residing coplanar with and at opposite ends of the first source and first drain structures; and a second gate dielectric residing between the first channel structure and the second gate electrode, wherein a thickness of the second gate dielectric is less than a thickness of the BOX layer.

A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

The present invention provides a manufacture method of a LTPS thin film transistor and a LTPS thin film transistor. The gate isolation layer is first etched to form the recess, and then the gate is formed on the recess so that the width of the gate is slightly larger than the width of the recess. Then, the active layer is implemented with ion implantation to form the source contact region, the drain contact region, the channel region and one transition region at least located between the drain contact region and the channel region. The gate isolation layer above the transition region is thicker than the channel region and can shield a part of the gate electrical field to make the carrier density here lower than the channel region to form a transition.