Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

A nitride semiconductor device includes: a substrate; a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer; a third semiconductor layer that includes a channel and is at least partially disposed above the second semiconductor layer; a gate electrode; a source electrode; a drain electrode; a first insulating layer disposed above the gate electrode and including nitride as a main component; and a second insulating layer disposed to cover a side surface of a groove that is provided in an edge termination area of the nitride semiconductor device. In the plan view, an end portion of the first insulating layer coincides with an end portion of the groove, or is positioned inside relative to the end portion of the groove and outside relative to an outermost periphery of the source electrode.

A semiconductor device has: a semiconductor substrate of a first conductivity type; a first region of the first conductivity type, provided in the semiconductor substrate and exposed at a main surface of the semiconductor substrate; a plurality of second regions of a second conductivity type, in contact with the first region, selectively provided in surface regions of the first region; a plurality of silicide films respectively in ohmic contact with the plurality of second regions; and an electrode in contact with the plurality of silicide films and forming a plurality of Schottky junctions with the first region. The plurality of silicide films have contact regions that are in contact with the first region.

Provided is a semiconductor device including: a drift region of a first conductivity type which is provided in a semiconductor substrate; an emitter region of the first conductivity type which is provided at a front surface of the semiconductor substrate, and which has a doping concentration higher than that of the drift region; a plurality of trench portions which are provided above the drift region; a trench contact portion which is provided in a mesa portion between the plurality of trench portions; and a plug region of a second conductivity type which is provided in contact with a lower end of the trench contact portion. The trench contact portion may have a main trench contact which extends in a trench extension direction in a top view, and a sub-trench contact which extends from the main trench contact in a direction different from the trench extension direction in the top view.

A power semiconductor device includes: a semiconductor body configured to conduct a forward load current between first and second load terminals; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure including: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current; and an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes, if a voltage between the first and second load terminals exceeds a maximal value and/or if the voltage between the second load terminal and the auxiliary control terminal is above a breakthrough voltage of the overload structure.

A transistor device includes a semiconductor substrate having a first major surface, a cell field, and an edge termination region laterally surrounding the cell field. The cell field includes elongate trenches that extend from the first major surface into the semiconductor substrate and that are positioned substantially parallel to one another such that one or more inner elongate trenches are arranged between two outermost elongate trenches and elongate mesas, each elongate mesa being formed between neighbouring elongate trenches. The elongate mesas include a drift region, a body region on the drift region and a source region on the body region. In a top view, one or both of the outermost elongate trenches has a different contour from the one or more inner elongate trenches.

A semiconductor device includes a semiconductor part, first to fourth electrodes, first and second insulating films. The semiconductor part includes a first layer of a first conductivity type and a second layer of a second conductivity type. The first and second electrodes are provided on back and front surfaces of the semiconductor part, respectively. The second layer is provided between the first layer and the second electrode. A plurality of the third electrodes extend into the first layer through the second layer. The fourth electrode extends into the first layer from the front side of the semiconductor part and surrounds the second layer. The first insulating film electrically insulates the third electrode from the semiconductor part. The second insulating film electrically insulates the fourth electrode from the semiconductor part. The second insulating film has a first thickness greater than a second thickness of the first insulating film.

A LDMOS including a semiconductor substrate, a gate oxide, a gate, field plate oxide layers and field plate barrier layers is disclosed. A first field plate oxide layer and a second field plate oxide layer are positioned atop the gate oxide with a spacing between them. A first field plate barrier layer and a second field plate barrier layer are positioned atop the first and the second field plate oxide layers, respectively. A third field plate barrier layer is positioned atop the first and the second field plate barrier layers and the spacing. A third field plate oxide layer is positioned atop the third field plate barrier layer. The third field plate oxide layer includes a first portion positioned atop the first field plate oxide layer and a second portion positioned atop the spacing. A fourth field plate barrier layer is positioned atop the third field plate oxide layer.

A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

An upper electrode is separated from a lower electrode inside a trench by an intermediate insulating film. A first resistor is connected between the upper electrode and the input terminal. A second resistor is connected between the lower electrode and the input terminal. Gate-emitter capacitance of the lower electrode is smaller than gate-emitter capacitance of the upper electrode.