A method includes: forming a barrier layer in a substrate; depositing a first dielectric layer over the substrate; forming a patterned mask layer over the first dielectric layer; patterning the first dielectric layer into a first sublayer of a gate dielectric layer; converting at least part of the patterned mask layer into a second sublayer of the gate dielectric layer; depositing a second dielectric layer adjacent to the first and second sublayers to serve as a third sublayer of the gate dielectric layer; and depositing a gate electrode over the gate dielectric layer.

A semiconductor device includes an n-type semiconductor layer, trenches, an insulating layer, a third electrode, and a p-type well region. The trenches extend in a first direction orthogonal to the thickness direction of the semiconductor layer and are spaced apart in a second direction orthogonal to the first direction. The insulating layer covers the trenches. The third electrode is formed in the insulating layer in contact with the first electrode. The well region is formed in the surface of the semiconductor layer. The well region extends in a direction intersecting the first direction and is one well regions spaced apart in the first direction. The surface of the semiconductor layer is in ohmic contact with the first electrode at the well surface of the well region. The surface of the semiconductor layer is in Schottky contact with the first electrode at an exposed surface between the well surfaces.

Disclosed herein is a Schottky barrier diode that includes: semiconductor substrate; a drift layer provided on the semiconductor substrate; a field insulating film covering an annular outer peripheral area of an upper surface of the drift layer; an anode electrode brought into Schottky-contact with a center area of the upper surface of the drift layer that is surrounded by the outer peripheral area, an end portion of the anode electrode being positioned on the field insulating film; a cathode electrode brough into ohmic contact with the semiconductor substrate; a first conductive member embedded in a first trench formed in the center area of the drift layer through an insulating film so as to be connected to the anode electrode; and a second conductive member contacting the field insulating film and electrically connected to the semiconductor substrate.

A semiconductor device manufacturing method including a reverse bias test for a device structure includes a step of applying a reverse bias voltage to the device structure, and a monitor step of monitoring a decrease rate of a leak current of the device structure at a time of applying the reverse bias voltage.

Disclosed are a bidirectional power device and a method for manufacturing the same. The bidirectional power device includes a semiconductor layer, a plurality of trenches located in the semiconductor layer, a gate dielectric layer located on an inner wall of each of the plurality of trenches, a control gate located at a lower portion of each of the plurality of trenches, a shield gate located at an upper portion of each of the plurality of trenches and an isolation layer located between the control gate and the shield gate. When the bidirectional power device is turned off, charges of a source region and a drain region are depleted by the shield gate through a shield dielectric layer, thereby improving voltage withstand property. When the bidirectional power device is turned on, the source region and/or the drain region and the semiconductor layer provide a low-impedance conduction path.

A leakage current is suppressed. A semiconductor device includes: a first anode electrode formed in a part of an upper surface of a gallium oxide layer of a first conductivity type; a semiconductor layer of a second conductivity type to cover a part of the gallium oxide layer and at least a part of the first anode electrode; and a second anode electrode to cover the semiconductor layer, wherein a plurality of trenches is formed in a surface layer of the gallium oxide layer, the first anode electrode is formed in the surface layer of the gallium oxide layer, the first anode electrode not overlapping the trenches in a plan view, and the semiconductor layer covers the gallium oxide layer in an inner portion of the trenches.

The present application relates to a semiconductor device and a preparation method therefor. The semiconductor device includes a semiconductor substrate, an insulating buried layer, a drift region, and a plurality of dielectric isolation structures. The insulating buried layer is located on the semiconductor substrate. The drift region is located on the insulating buried layer. A drain region is provided on part of the upper surface of the drift region. The plurality of dielectric isolation structures are located in the drift region and on the insulating buried layer, and are spaced apart from each other in a direction towards the drain region. At least one dielectric isolation structure protrudes from the insulating buried layer and is bent towards the drain region.

An integrated circuit (IC) includes electronic components monolithically disposed on and/or in a semiconductor substrate, the electronic components including at least a humidity sensor device, a metallization stack, and an exposed conductive surface that is electrically connected with the humidity sensor device by the metallization stack of the IC. The exposed conductive surface is exposed to an ambient gas whose relative humidity is to be measured. In some designs, the humidity sensor device includes a PN junction, and the exposed conductive surface is electrically connected with the cathode of the PN junction. The exposed conductive surface may be an exposed bond pad of the IC.

A semiconductor device includes: a substrate and backward and forward diodes. Each backward diodes includes: a first channel layer; a first barrier layer; a first gate electrode; a first gate semiconductor layer; and a first source electrode and a first drain electrode that are disposed at opposite sides of the first gate electrode. The forward diode includes: a second channel layer; a second barrier layer; a second gate electrode; a second gate semiconductor layer; and a second source electrode and a second drain electrode that are disposed at opposite sides of the second gate electrode. The second source electrode is connected to the second gate electrode, and a first drain electrode of the backward diodes is connected with a second source electrode of the forward diode. The band gaps of the first (second) channel layer and the first (second) barrier layers are different.

A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.