The semiconductor device comprises a semiconductor body with a top side, a main electrode on the top side and a gate electrode. The semiconductor body comprises a drift layer of a first conductivity type, a first base region of a second conductivity type, a second base region of the first conductivity type, a first contact region of the first conductivity type and a second contact region of the second conductivity type. The second base region has a greater doping concentration than the drift layer. The first contact region adjoins the first base region and the top side. The second contact region adjoins the second base region and the top side. The main electrode is in electrical contact with the first and the second contact region. In a first lateral direction, at least a portion of the gate electrode is arranged between the first contact region and the second contact region.

A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

A nitride semiconductor device includes: a substrate; a first semiconductor layer of a first conductivity type disposed above the substrate; a second semiconductor layer of a second conductivity type disposed above the first semiconductor layer; a third semiconductor layer that includes a channel and is at least partially disposed above the second semiconductor layer; a gate electrode; a source electrode; a drain electrode; a first insulating layer disposed above the gate electrode and including nitride as a main component; and a second insulating layer disposed to cover a side surface of a groove that is provided in an edge termination area of the nitride semiconductor device. In the plan view, an end portion of the first insulating layer coincides with an end portion of the groove, or is positioned inside relative to the end portion of the groove and outside relative to an outermost periphery of the source electrode.

An integrated circuit (IC) structure includes two active areas extending in a first direction, two gate structures extending in a second direction, a first metal segment extending in the second direction in a first metal layer, second and third metal segments extending in the first direction in a second metal layer, and a gate via structure extending from the third metal segment to one of the gate structures. The gate structures overlie the active areas, the first metal segment overlies each of the active areas between the gate structures, the second metal segment overlies a first active area and overlies and is electrically connected to the first metal segment, and the first and second metal segments are electrically connected to the second active area, isolated from the first active area between the gate structures, and connected to the first active area outside the gate structures.

The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.

A microelectronic device includes a substrate, at least two doped well regions, an epitaxial structure, and at least two power elements. The doped well regions are disposed in the substrate, and are spaced apart from each other. Each of the doped well regions has a doping type opposite to that of the substrate. The epitaxial structure is disposed on the substrate, and is in contact with the doped well regions. The power elements are disposed on the epitaxial structure opposite to the substrate, and are cascade connected with each other. A low potential terminal of each of the power elements is electrically connected to a respective one of the doped well regions. A method for making the microelectronic device is also provided.

A method of manufacturing an IC structure includes: forming first and second active areas; forming first and second gate structures overlying the first and second active areas; forming a first source/drain via structure on a first portion of the first active area between the first and second gate structures; forming a second source/drain via structure on a first portion of the second active area extending beyond the first and second gate structures; forming a first metal segment in a first metal layer, contacting the first source/drain via structure, and overlying the second active area; and forming a second metal segment in a second metal layer and electrically connecting the first portion of the first active area to the first portion of the second active area, the first and second metal segments being electrically isolated from a second portion of the second active area between the first and second gate structures.

Semiconductor structures and methods are provided. An exemplary semiconductor structure according to the present disclosure includes a semiconductor substrate including a first region and a second region surrounding the first region, a III-V semiconductor layer disposed directly over the first region, a compound semiconductor device formed in and over the III-V semiconductor layer, a first plurality of conductive features disposed over and electrically coupled to a source contact of the compound semiconductor device, and a seal ring disposed directly over the second region and comprising a second plurality of conductive features, a top surface of a topmost conductive feature of the first plurality of conductive features is higher than a top surface of a topmost conductive feature of the second plurality of conductive features.

In an embodiment, a device includes: a gallium nitride device on a substrate, the gallium nitride device including an electrode; a dielectric layer on and around the gallium nitride device; an isolation layer on the dielectric layer; a semiconductor layer on the isolation layer, the semiconductor layer including a silicon device; a through via extending through the semiconductor layer, the isolation layer, and the dielectric layer, the through via electrically and physically coupled to the electrode of the gallium nitride device; and an interconnect structure on the semiconductor layer, the interconnect structure including metallization patterns electrically coupled to the through via and the silicon device.

A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.