In one aspect, a diode comprises: a semiconductor layer having a first side and a second side opposite the first side, the semiconductor layer having a thickness between the first side and the second side, the thickness of the semiconductor layer being based on a mean free path of a charge carrier emitted into the semiconductor layer; a first metal layer deposited on the first side of the semiconductor layer; and a second metal layer deposited on the second side of the semiconductor layer.

Semiconductor device with a semiconductor body that includes a clamping structure including a pn junction diode and a Schottky junction diode serially connected back to back between a first contact and a second contact. A breakdown voltage of the pn junction diode is greater than 100 V and a breakdown voltage of the Schottky junction diode is greater than 10 V.

A diode is provided which includes at least one diode element which has a plurality of N-type regions and a plurality of P-type regions, the N-type regions and the P-type regions being alternately arranged in series to form PN junctions, and an insulated substrate which has electric insulation. The N-type regions and the P-type regions are formed on the insulated substrate.

In a semiconductor device such as a three-phase one-chip gate driver IC, HVNMOSs configuring two set and reset level shift circuits are disposed on non-opposed surfaces, and it is thereby possible to reduce the amount of electrons flowing into drains of HVNMOSs of another phase due to a negative voltage surge. Also, distances from an opposed surface on the opposite side to the respective drains of the HVNMOSs configuring the two set and reset level shift circuits are made equal to or more than 150 m, and it is thereby possible to prevent a malfunction of a high side driver circuit of another phase to which no negative surge is applied.

A method of manufacturing a semiconductor structure includes forming on a substrate, at intervals in a first direction, a first trench, a second trench, and a third trench, forming a first oxide layer in the first trench, forming a second oxide layer in the second trench, and forming a third oxide layer in the third trench. The method also includes forming a first semiconductor material layer in the first trench, forming a second semiconductor material layer in the second trench, and forming a third semiconductor material layer in the third trench. The method further includes forming a mask layer, performing a first etching process on the mask layer to form a first opening and a second opening, performing a second etching process at the second opening to form a third surface on the substrate, and forming a first doped region adjacent to the third surface exposed by the second opening.

Disclosed are a micro light emitting diode display panel, a method of manufacturing the same, and a display device. The micro light emitting diode display panel includes a driving circuit substrate, a plurality of micro light emitting diodes, and a protective layer. The plurality of micro light emitting diodes are disposed on a first surface of the driving circuit substrate. The protective layer is disposed at least on the first surface of the driving circuit substrate and covers the micro light emitting diodes. A material of the protective layer is selected from a Parylene system or an acrylic acid system.

The disclosure relates to a semiconductor die, comprising: a first diode chain having a number n.sub.1 of diode junctions connected in series, where n.sub.11; a second diode chain having a number n.sub.2 of diode junctions connected in series, where n.sub.21; the first diode chain and the second diode chain to be biased with the same current as a temperature sensor, wherein the first diode chain and the second diode chain differ from each other in their respective number n.sub.1, n.sub.2 of junctions and/or in a doping concentration of at least one of the junctions.

A semiconductor device according to one embodiment includes a first electrode, a second electrode, a semiconductor layer between the first electrode and the second electrode, a plurality of first semiconductor regions on a side of the first electrode, a plurality of second semiconductor regions on surface sides of the plurality of first semiconductor regions, and a plurality of PIN diode regions provided on the side of the first electrode in the semiconductor layer, the plurality of PIN diode regions extending in a third direction orthogonal to the first direction and the second direction, the plurality of PIN diode regions electrically connected to at least one of the plurality of first semiconductor regions and at least one of the plurality of second semiconductor regions.

An electronic device is provided comprising a substrate and at least one first input/output pad, each first pad being coupled to the substrate by an assembly, each assembly comprising first and second wells, the first well being located in the second well, the second well being located in the substrate, the substrate and the first well being doped with a first conductivity type, the second well being doped with a second conductivity type opposite to the first conductivity type, each assembly being configured so that the threshold voltage of the diode formed by the first and second wells is lower than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type P, or higher than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type N.

A semiconductor device includes a plurality of tunnel diodes, each of which includes a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type that is provided above the first semiconductor region, the second semiconductor region being a nanowire shape; an insulating film provided around a side surface of the second semiconductor region; a plurality of first electrodes, each coupled to the first semiconductor region; and a plurality of second electrodes, each coupled to the second semiconductor region, wherein the second electrode has a first surface that faces the side surface of the second semiconductor region across the insulating film, and a diameter of a second semiconductor region of a first tunnel diode of the plurality of tunnel diodes is different from a diameter of a second semiconductor region of a second tunnel diode.