According to one aspect of the present disclosure, a semiconductor electrostatic discharge (ESD) device includes a substrate. In some embodiments one or more dielectric layers disposed on the substrate. In some embodiments, there are one or more polysilicon diodes disposed within the one or more dielectric layers. In some embodiments, there is a metallization layer with two or more metal interconnect pads. In some embodiments, there are two or more vias, wherein a first via is connected to a first metal interconnect pad and a second via is connected to a second metal interconnect pad, wherein the polysilicon diodes are connected to the two or more vias, wherein the one or more polysilicon diodes are configured to provide ESD protection at the metal interconnect pads.

A semiconductor device includes a first diode having a first cathode and a first anode, wherein the first cathode is floating. The semiconductor device includes a second diode having a second cathode and a second anode, wherein the first anode is coupled to the second anode with the second cathode connected to a first supply voltage. The semiconductor device includes a third diode having a third cathode and a third anode, wherein the third cathode is connected to the first anode at an input/output pin, with the third anode connected to a second supply voltage. The second anode is coupled to a circuit that is powered by the first supply voltage and the second supply voltage. The first diode has a first size and the second diode has a second size, and the first size is substantially greater than the second size.

A semiconductor chip of a TVS diode includes a first pin junction portion of a first polarity direction and a diode pair region. The diode pair region includes a first reverse pin junction portion of a second polarity direction provided spaced apart from the first pin junction portion in a plan view, and a pn junction portion of the first polarity direction that forms a diode pair with the first reverse pin junction portion. The first pin junction portion includes a p-type first-terminal-side high-concentration region, an n-type first-terminal-side low-concentration region at a position overlapping the first-terminal-side high-concentration region in the plan view, an n-type first-terminal-side contact region, and a p-type first buffer region in contact with the first-terminal-side high-concentration region between the first-terminal-side high-concentration region and the first-terminal-side low-concentration region in a thickness direction of the semiconductor chip.

The disclosure provides a semiconductor package having an isolation structure comprising an isolation trench filled with dielectric material, where the isolation structure traverses the thickness of the isolated semiconductor dies.

Disclosed herein is a Schottky barrier diode that includes: semiconductor substrate; a drift layer provided on the semiconductor substrate; a field insulating film covering an annular outer peripheral area of an upper surface of the drift layer; an anode electrode brought into Schottky-contact with a center area of the upper surface of the drift layer that is surrounded by the outer peripheral area, an end portion of the anode electrode being positioned on the field insulating film; a cathode electrode brough into ohmic contact with the semiconductor substrate; a first conductive member embedded in a first trench formed in the center area of the drift layer through an insulating film so as to be connected to the anode electrode; and a second conductive member contacting the field insulating film and electrically connected to the semiconductor substrate.

A method of making a semiconductor device is provided. A monolithic die having at least two semiconductor dies is provided. Each of the at least two semiconductor dies includes a substrate and an epitaxial layer formed on the substrate. An isolation structure is formed electrically isolating two semiconductor dies of the at least two semiconductor dies. The isolation structure traverses the thickness of the substrate and the epitaxial layer and includes a first isolation trench.

An integrated circuit includes a first horizontal conductor and a second horizontal conductor. The integrated circuit includes a first diode between a first first-type block and a first second-type block, a second diode between a second first-type block and a second second-type block, and a third diode between a third first-type block and a third second-type block. The first first-type block and the first second-type block are aligned along a first column. The second first-type block and the second second-type block are aligned along a second column. The third first-type block and the third second-type block are aligned along a third column. The second first-type block is connected to the first second-type block through the second horizontal conductor. The third first-type block is conductively connected to the second second-type block through the first horizontal conductor.

The present specification discloses a semiconductor device including dual trenches and a method of fabricating the same. The semiconductor device includes a first region where a plurality of first semiconductor elements are provided on a substrate, a second region where a plurality of second semiconductor elements are provided on the substrate, an isolation region provided in the substrate between the first region and the second region, shallow trenches formed in the substrate of the first region and the second region, a shallow trench insulating film formed inside each of the shallow trenches, a deep trench formed in the substrate of the isolation region, and a deep trench insulating film formed inside the deep trench, in which a well tap structure is not provided in the substrate between the first region and the second region.

A quasi-vertical JBS diode and a monolithic integrated three-phase DRU are provided. The quasi-vertical JBS diode includes a Si substrate, a N+ GaN conductive layer and an N-type GaN drift layer sequentially disposed from bottom to top. A top region of the N-type GaN drift layer defines groove structures distributed concentrically and annularly, and a Mg-doped P-type BN material is disposed on an inside of each of the groove structures and a side of the N-type GaN drift layer. An anode is disposed on a surface of the N-type GaN drift layer defining the groove structures. A cathode is disposed on a surface of the N+ GaN conductive layer at intervals around the N-type GaN drift layer. The monolithic integrated three-phase DRU includes three AC input terminals, two rectified DC output terminals and diode groups corresponding to six rectifier bridge arms. The diodes each are the quasi-vertical JBS diode.

A diode structure includes a first stack of semiconductor layers, wherein the first stack of semiconductor layers includes a plurality of first semiconductor layers arranged in an alternating arrangement with a plurality of second semiconductor layers. The diode structure further includes a second stack of semiconductor layers, wherein the second stack of semiconductor layers includes a plurality of third semiconductor layers arranged in an alternating arrangement with a plurality of fourth semiconductor layers. The diode structure further includes a fifth semiconductor layer between the first stack of semiconductor layers and the second stack of semiconductor layers, wherein a composition of the fifth semiconductor layer is different from each of the plurality of first, second, third and fourth semiconductor layers. The diode structure further includes an n-type doped region in the first stack of semiconductor layers; and a p-type doped region in the second stack of semiconductor layers.