Semiconductor Device and Process for Making Same

Abstract

A method of making a semiconductor device is provided. A monolithic die having at least two semiconductor dies is provided. Each of the at least two semiconductor dies includes a substrate and an epitaxial layer formed on the substrate. An isolation structure is formed electrically isolating two semiconductor dies of the at least two semiconductor dies. The isolation structure traverses the thickness of the substrate and the epitaxial layer and includes a first isolation trench.

Claims

1. A method of making a semiconductor device, comprising; providing a monolithic die having at least two semiconductor dies, each of the at least two semiconductor dies including a substrate and an epitaxial layer formed on the substrate; and forming an isolation structure electrically isolating two semiconductor dies of the at least two semiconductor dies, the isolation structure traversing thickness of the substrate and the epitaxial layer and comprising a first isolation trench.

2. The method of claim 1, wherein forming the isolation structure comprises: forming, at a top surface of the epitaxial layer, the first isolation trench extending from the top surface of the epitaxial layer to a bottom surface of the substrate.

3. The method of claim 2, further comprising: forming a layer of a first dielectric material on the top surface of the epitaxial layer, and filling and covering the first isolation trench.

4. The method of claim 3, further comprising: forming a second dielectric material on the bottom surface of the substrate and encapsulating the two semiconductor dies.

5. The method of claim 4, wherein the first dielectric material is different from the second dielectric material.

6. The method of claim 1, wherein forming the isolation structure comprises: forming, at a bottom surface of the substrate, the first isolation trench extending from the bottom surface of the substrate to a top surface of the epitaxial layer.

7. The method of claim 6, further comprising: forming a layer of a first dielectric material on the bottom surface of the substrate, and filling and covering the first isolation trench.

8. The method of claim 1, wherein forming the isolation structure comprises: forming, at a top surface of the epitaxial layer, the first isolation trench extending from the top surface of the epitaxial layer into the substrate; filling the first isolation trench with a first dielectric material; forming, at a bottom surface of the substrate, a second isolation trench extending from the bottom surface of the substrate toward the epitaxial layer, the second isolation being connected to the first isolation trench in the substrate; and filling the second isolation trench with a second dielectric material.

9. The method of claim 8, further comprising: forming a plurality of sub-trenches in the first isolation trench.

10. The method of claim 8, wherein the first isolation trench and the second isolation trench have different widths.

11. The method of claim 8, wherein the first dielectric material is different from the second dielectric material.

12. The method of claim 1, further comprising: forming, in each of the at least two semiconductor die, a channel extending from a bottom surface of the substrate into the substrate; and forming a metal layer in the channel and on the bottom surface of the substrate.

13. The method of claim 12, further comprising: forming a plurality of sub-channels in the channel.

14. The method of claim 12, wherein the channel is extended from the bottom surface of the substrate into the epitaxial layer through the substrate.

15. A method comprising: providing two semiconductor dies adjacent to each other, each of the two semiconductor dies including a substrate and an epitaxial layer formed on the substrate; and forming an isolation trench extending from a top surface of the epitaxial layer to a bottom surface of the substrate to form an isolation structure, the isolation structure electrically isolating the two semiconductor dies, wherein the isolation trench is filled with a dielectric material.

16. The method of claim 15, wherein forming the isolation trench comprises: forming the isolation trench at the top surface of the epitaxial layer.

17. The method of claim 15, wherein forming the isolation trench comprises: forming the isolation trench at the bottom surface of the substrate.

18. A method comprising: providing two semiconductor dies adjacent to each other, each of the two semiconductor dies including a substrate and an epitaxial layer formed on the substrate; forming, at a top surface of the epitaxial layer, a first isolation trench extending from the top surface of the epitaxial layer into the substrate; forming, at a bottom surface of the substrate, a second isolation trench extending from the bottom surface of the substrate toward the epitaxial layer and connected to the first isolation trench in the substrate; and filling the first isolation trench with a first dielectric material and filling the second isolation trench with a second dielectric material, the first isolation trench and the second isolation trench forming an isolation structure electrically isolating the two semiconductor dies.

19. The method of claim 18, wherein the first isolation trench and the second isolation trench have different widths.

20. The method of claim 18, wherein the first dielectric material is different from the second dielectric material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] FIG. 1 provides a cross-sectional view of the circuit element exemplified in the embodiments of the present invention;

[0020] FIG. 2a-2k provides a demonstration of the manufacturing process according to the semiconductor device of the first embodiment;

[0021] FIG. 3 provides a circuit layout of the circuit elements employed in the embodiments of the present invention;

[0022] FIG. 4a-4k provides a demonstration of the manufacturing process according to the semiconductor device of the second embodiment;

[0023] FIGS. 5a and 5b provide a cross-sectional view of the circuit element having a channel structure as exemplified in the embodiments of the present invention;

[0024] FIG. 6a-6k provides a demonstration of the manufacturing process according to the semiconductor device of the third embodiment; and

[0025] FIG. 7 provides a cross sectional view of the semiconductor device according to the fourth embodiment.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0026] The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the disclosure. In addition, the drawings are for illustrative purpose only and are not drawn based on the original dimensions, so the size and proportion may not be consistent with the actual dimensions.

[0027] The terms top, bottom and sides are used in reference to the attached drawing figures and should not be construed as indication of orientation limitations when describing a physical device.

[0028] The term photolithography refers to a process used in microfabrication to pattern parts on a thin film or the bulk of a wafer, in which a series of treatments including applying photoresist, light exposure, development and curing are performed in the order.

[0029] The term front-end process refers to the processing steps of the semiconductor dies that usually starts with the fabrication of the circuit elements embedded in and on the dies and ends with the formation of the passivation layer. The term front-end etching process refers to the etching process adopted during the front-end process which is usually used in forming patterns on the surface of the dies. Typical front-end etching process may include, for example, wet chemical etching.

[0030] The term back-end process refers to the processing steps of the semiconductor dies that usually starts at the completion of the front-end process and usually contains the steps of back-grinding, die bonding, wire bonding, molding, sawing and testing. The term back-end etching process refers to the etching process adopted during the back-end process which can be used in forming patterns on the bottom of the dies. Typical back-end etching process includes, for example, plasma etching or sawing.

[0031] Schottky trenched diodes are employed in the embodiments of the present invention as the circuit element for demonstrative purpose where the semiconductor die includes a heavily doped semiconductor substrate with a mildly doped semiconducting epitaxial layer grown thereon. The substrate typically has an electrical resistance of around 1 to 5 mohm*cm and is deemed electrically conductive. To make the cathode and anode accessible on the top surface of the dies, the cathode is configured to connect directly with the substrate so as to direct the electrons, from the heavily doped semiconductor substrate that mainly come from the anode, to the cathode.

[0032] More specifically, as shown in FIG. 1, for each unit of the diodes, an anode region 140 occupies a portion of the epitaxial layer 2 and a cathode region 130 occupies another portion of the epitaxial layer 2. The anode region 140 contains a plurality of trench filled with polysilicon which is embedded in the epitaxial layer, and a first metal layer 10, e.g., Titanium, is sputtered on the surface of the epitaxial layer 2 for forming Schottky junction in the anode region 140. A second metal layer 11, e.g., AlSiCu, is deposited on the first metal layer 10. The cathode region 130 contains a recess 9 excavated from the surface of the epitaxial layer 2 to the surface of the semiconductor substrate 3 and filled with the first metal layer 10 and the second metal layer 11. A passivation layer 12 and a third metal layer 13, e.g., Ni/Au, are applied subsequently on and/or around at least a portion of the second metal layer 11.

[0033] Referring to the first embodiment as shown in FIG. 2a-2k. Starting with a monolithic die 1, a silicon substrate 3 having a thickness of about 700 m is provided. In this embodiment, the silicon substrate 3 is heavily doped with N-type dopants with a doping concentration in a range of 1.2210.sup.19 to 8.1910.sup.19 atoms/cm.sup.3. The epitaxial layer 2, having a thickness of about 40 m, is grown on the upper side of the silicon substrate 3, in which the epitaxial layer has a doping concentration in a range of 1.5610.sup.16 to 4.9510.sup.15 atoms/cm.sup.3. The selection of the N-type dopants may include, for example, arsenic or phosphorous. Before fabricating the circuit element 6 of the die, the isolation trench 16 is excavated from the top surface of the epitaxial layer 2 in the non-active region 120 by using photoresist and photo patterning processes to a depth of around 70 m, and the width of the isolation trench 120 is around 1.2 m. The isolation trench 16 is then filled with dielectric material 4, such as silicon dioxides through chemical vapor deposition (CVD), as illustrated in FIG. 2a. In this embodiment, more than one isolation trench can be formed using the same photolithography process.

[0034] Circuit elements 6 are then fabricated in the way embedded in and on the epitaxial layer 2 of the active region 110. In this embodiment, Schottky trenched diodes is fabricated by using photolithography technique where a series of treatment including photoresist application, light exposure, selective etching, photoresist removal and trench etching is performed, resulting in an array of trench in the anode region 140 and cathode region 130. A layer of gate oxide may be formed along the wall of the trenches by thermal oxidation. Then, polysilicon is deposited using CVD so as to fill the trenches as formed in the anode region 140, as illustrated in FIG. 2b. A polysilicon etch-back is performed thereafter to remove the excess portion of the polysilicon, while a layer of polysilicon may be retained around the wall of the trench in the cathode region 130. An interlayer dielectric (ILD) 7 is then deposited on at least a portion of the surface of the semiconductor die 1, as shown in FIG. 2c.

[0035] As illustrated in FIG. 2d, a photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the anode region 8 is formed. The photoresist is removed upon the formation of the anode recess 8.

[0036] As illustrated in FIG. 2e, another photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the cathode region 9 is formed. The photoresist is removed upon the formation of the cathode recess 9.

[0037] In this embodiment, the bottom of the anode recess 8 reaches the surface of the epitaxial layer 2, while the bottom of the cathode recess 9 reaches the surface of the substrate 3. In some embodiments of the present invention, the bottom of the cathode 9 recess may lie above the substrate 3.

[0038] A first metal layer 10 is then formed complying with the topology of the die surface resulted from the previous processes. The first metal layer 10, e.g. using Titanium sputtering, can form Schottky junction at the anode recess 8 and form ohmic junction at the cathode recess 9. Further treatment such as a rapid thermal process (RTP) may be further applied to the first metal layer 10. A second metal layer 11, e.g. using AlSiCu sputtering, is then formed on the first metal layer 10 for electrical interconnection amongst different isolated dies (as will be shown in the later stage). A cross-sectional view at this stage is shown in FIG. 2f.

[0039] As shown in FIG. 2g, the second metal layer 11 and 10 are then patterned as desired using photolithography technique including photoresist application, selective etching and photoresist removal. A sintering process may be further conducted to adjust the energy barrier height of the Schottky junction.

[0040] As shown in FIG. 2h, a passivation layer 12, e.g., polyimide, is applied on or around at least a portion of the second metal layer 11 to protect the circuit elements. The pattern of the passivation layer 12 can be achieved by using photolithography technique. A third metal layer 13 is then applied on the portion of the die surface designated for connecting the soldering material (not shown in the figures). The third metal layer 13 can be a chemical plating layer so that the photolithography process is not needed for forming the intended pattern. For example, a composite layer of Ni/Au can be selected as the material of the third metal layer 13.

[0041] After completing the front-end process, the semiconductor die 1 is flipped over for backend processing. As shown in FIG. 2i, a back grinding process takes place which thins the die until the exposure of the dielectric layer 4 and thereby separates the monolithic die into isolated semiconductor dies 5. Each isolated semiconductor dies are then encapsulated with molding compound 14, such as epoxy resin, on its four sides and bottom, as illustrated in FIG. 2j. The final form of the semiconductor device of this embodiment 100 is illustrated in FIG. 2k. The semiconductor device will be sawed for singulation and further testing.

[0042] Referring to FIG. 3, a circuit layout where four diodes (i.e., isolated dies 5) electrically connected to serve as a bridge rectifier is illustrated. It should be noted that other class of circuit and circuit element can be adopted and benefit from the present invention.

[0043] Referring to the second embodiment as shown in FIG. 4a-4k. A monolithic die having a substrate 3 grown on its top with an epitaxial layer 2 is prepared. Circuit elements 6 are formed in the way embedded in and on the epitaxial layer. The fabrication process of the circuit element is illustrated as follows. In this embodiment, Schottky trenched diodes is fabricated by using photolithography technique where a photoresist is firstly applied on the surface of the layer 4, as shown in FIG. 4a. Followed by light exposure, selective etching, photoresist removal and trench etching, an array of trench in the anode region 140 and cathode region 130 is formed. A layer of gate oxide may be further formed along the wall of the trenches by thermal oxidation. Then, polysilicon is deposited using CVD so as to fill the trenches as formed in the anode region 140, as illustrated in FIG. 4b. A polysilicon etch-back is performed thereafter to remove the excess portion of the polysilicon. An interlayer dielectric (ILD) 7 is then deposited on at least a portion of the surface of the semiconductor die 1, as shown in FIG. 4c.

[0044] As illustrated in FIG. 4d, a photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the anode region 8 is formed. The photoresist is removed upon the formation of the anode recess.

[0045] As illustrated in FIG. 4e, another photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the cathode region 9 is formed. The photoresist is removed upon the formation of the cathode recess.

[0046] In this embodiment, the bottom of the anode recess 8 reaches the surface of the epitaxial layer 2, while the bottom of the cathode recess 9 reaches the surface of the substrate 3. In some embodiments of the present invention, the bottom of the cathode 9 recess may lie above the substrate 3.

[0047] A first metal layer 10 is then formed complying with the topology of the die surface resulted from the previous processes. The first metal layer 10, e.g. using Titanium sputtering, can form Schottky junction at the anode recess 8 and form ohmic junction at the cathode recess 9. Further treatment such as a rapid thermal process (RTP) may be further applied to the first metal layer 10. A second metal layer 11, e.g. using AlSiCu sputtering, is then formed on the first metal layer 10 for electrical interconnection amongst different isolated dies (as will be shown in the later stage). A cross-sectional view at this stage is shown in FIG. 4f.

[0048] As shown in FIG. 4g, the second metal layer 11 and 10 are then patterned as desired using photolithography technique including photoresist application, selective etching and photoresist removal. A sintering process may be further conducted to adjust the energy barrier height of the Schottky junction.

[0049] As shown in FIG. 4h, a passivation layer 12, e.g., polyimide, is applied on or around at least a portion of the second metal layer 11 to protect the circuit elements. The pattern of the passivation layer 12 can be achieved by using photolithography technique. A third metal layer 13 is then applied on the portion of the die surface designated for connecting the soldering material (not shown in the figures). The third metal layer 13 can be a chemical plating layer so that the photolithography process is not needed for forming the intended pattern. For example, a composite layer of Ni/Au can be selected as the material of the third metal layer 13.

[0050] It should be noted that no front-end etching process is performed on the non-active region in the second embodiment. After completing the front-end process, the semiconductor die 1 is flipped over, and a back grinding process takes place that thins the die to a thickness of around 70 m. Then, a back-end etching process, such as plasma etching or sawing, is used to form the isolation trench 17 which is excavated from backside of the die to the ILD layer 7 on the front side of the die and thereby separating the monolithic die into isolated semiconductor dies 5. In the situation where the plasma etching process is employed, the plasma etching process is carried out along with the photolithography technique to form the isolation trench 17 at the designated portion of the non-active region 120. In this embodiment, a width of around 75 m of the isolation trench 17 is formed with the plasma etching. An illustration of the above processing steps are shown in FIG. 4i. The molding compound 14, such as epoxy resin, is then applied to fill the isolation trench 17 and encapsulate the isolated dies 5 on its sides and bottom, as illustrated in FIG. 4j. The final form of the semiconductor package 200 of this embodiment is illustrated in FIG. 4k.

[0051] The front-end etching process is known to have its limitation in forming the deep trench. In general, advanced equipment will be needed if the trench with the depth of over 40 m is intended. By forming the trench with back-end etching process rather than the front-end etching process, this embodiment is advantageous in the aspect to be free from the need of the advanced equipment.

[0052] Referring to FIG. 5a, in some applications, a channel 15 filled with a fourth metal 18 is introduced in the cathode region 130 of the substrate, where the channel 15 is formed using the backside etching process (e.g., plasma etching) by excavating from the bottom of the substrate 3 up to the junction between the substrate 3 and the epitaxial layer 2. Alternatively, the channel 15 may extend up to the height protruded into the epitaxial layer 2, as illustrated in FIG. 5b. In either cases, the cathode recess 9 should be in conjunction with the fourth metal 18.

[0053] The channel 15 can be formed as a single channel or an array of channel as long they are resided under the cathode region 130 of the substrate. The shape of the channel 15 can be polygonal columnar or cylindrical. A fourth metal layer 18 is plated in the channel 15 and on the bottom surface of the substrate 3 after the formation of the channel. The process of forming the channel 15 and filling of the fourth metal 18 may be conducted prior to the formation of the isolation trench structure during the back-end etching process. By introducing the channel 15 filled with the fourth metal layer 18 in the cathode region 130 of the substrate, the forward voltage drop can be further improved.

[0054] Referring to the third embodiment as shown in FIG. 6a-6k. Before fabricating the circuit element 6 of the die, a first isolation trench 16 is excavated from the top surface of the epitaxial layer 2 in the non-active region 120 by using photoresist and photo patterning processes. The first isolation trench 16 is then filled with dielectric material 4, such as silicon dioxides through chemical vapor deposition (CVD), as illustrated in FIG. 6a. In this embodiment, more than one isolation trench can be formed using photolithography process.

[0055] In this embodiment, the first isolation trench 16 may be formed with a depth of around 40 m and a width of around 1.2 m. A first dielectric material 4, such as silicon dioxide or polysilicon, is filled into the first isolation trench 16 and thus forms a first isolation structure.

[0056] Circuit elements 6 are then fabricated in the way embedded in and on the epitaxial layer 2 of the active region 110. In this embodiment, Schottky trenched diodes is fabricated by using photolithography technique where a series of treatment including photoresist application, light exposure, selective etching, photoresist removal and trench etching is performed, resulting in an array of trench in the anode region 140 and cathode region 130. A layer of gate oxide may be formed along the wall of the trenches by thermal oxidation. Then, polysilicon is deposited using CVD so as to fill the trenches as formed in the anode region 140, as illustrated in FIG. 6b. A polysilicon etch-back is performed thereafter to remove the excess portion of the polysilicon, while a layer of polysilicon may be retained around the wall of the trench in the cathode region 130. An interlayer dielectric (ILD) 7 is then deposited on at least a portion of the surface of the semiconductor die 1, as shown in FIG. 6c.

[0057] As illustrated in FIG. 6d, a photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the anode region 8 is formed. The photoresist is removed upon the formation of the anode recess 8.

[0058] As illustrated in FIG. 6e, another photoresist (PR) is applied on the ILD layer 7. Followed by light exposure and selective etching, a recess of the cathode region 9 is formed. The photoresist is removed upon the formation of the cathode recess 9.

[0059] In this embodiment, the bottom of the anode recess 8 reaches the surface of the epitaxial layer 2, while the bottom of the cathode recess 9 reaches the surface of the substrate 3. In some embodiments of the present invention, the bottom of the cathode 9 recess may lie above the substrate 3.

[0060] A first metal layer 10 is then formed complying with the topology of the die surface resulted from the previous processes. The first metal layer 10, e.g. using Titanium sputtering, can form Schottky junction at the anode recess 8 and form ohmic junction at the cathode recess 9. Further treatment such as a rapid thermal process (RTP) may be further applied to the first metal layer 10. A second metal layer 11, e.g. using AlSiCu sputtering, is then formed on the first metal layer 10 for electrical interconnection amongst different isolated dies (as will be shown in the later stage). A cross-sectional view at this stage is shown in FIG. 6f.

[0061] As shown in FIG. 6g, the second metal layer 11 and the first metal layer 10 are then patterned as desired using photolithography technique including photoresist application, selective etching and photoresist removal. A sintering process may be further conducted to adjust the energy barrier height of the Schottky junction.

[0062] As shown in FIG. 6h, a passivation layer 12, e.g., polyimide, is applied on or around at least a portion of the second metal layer 11 to protect the circuit elements. The pattern of the passivation layer 12 can be achieved by using photolithography technique. A third metal layer 13 is then applied on the portion of the die surface designated for connecting the soldering material (not shown in the figures). The third metal layer 13 can be a chemical plating layer so that the photolithography process is not needed for forming the intended pattern. For example, a composite layer of Ni/Au can be selected as the material of the third metal layer 13.

[0063] After completing the front-end process, the die is flipped over and back grounded to a thickness of around 70 m that followed by a back-end etching process which forms a second isolation trench 17 to a height in conjunction with the first isolation trench 16 from the backside of the die. In the situation where the plasma etching process is employed as the back-end etching process, the plasma etching process is carried out along with the photolithography technique to form the second isolation trench 17 at the designated portion of the non-active region 120, as shown in FIG. 6i. The second isolation trench 17 can be formed by plasma etching with a width of around 75 m. A second dielectric material 14 such as molding compound is then filled into the second isolation trench 17 and encapsulates the isolated semiconductor dies 5 with its sides and bottom, where the portion filled in the second isolation trench 17 of the molding compound forms the second isolation structure, as shown in FIG. 6j. The first isolation structure and the second isolation structure jointly form an isolation structure traversing the thickness of the isolated semiconductor dies 5. The final form of the semiconductor device 300 of this embodiment is illustrated in FIG. 6k.

[0064] The first isolation trench 16 may include more than one trench structure. In one specific embodiment, the first isolation trench 16 may include a plurality of sub-trench 19 structure, the manufacturing process of forming the plurality of sub-trench 19 can be the same to that of the formation of the single trench structure except that the pattern of the photoresists are different; a thermal oxidation is further carried out to oxidize the remaining mesa portion 20 which set apart each sub-trenches 19 within the non-active region 120. A first dielectric material 4, e.g., silicon dioxides or polysilicon, may be filled into the plurality of sub-trench 19 using CVD, subsequently. In this specific embodiment, the plurality of the sub-trench 19, the oxidized mesa portion 20 and the first dielectric material 4, collaborately, make up the first isolation trench 16. The final form 400 of this embodiment is shown in FIG. 7.

[0065] The reliability in high temperature can be further improved with the third embodiment. Because less amount of the molding compound is filled into the second isolation trench, the thermal stress incurred by the difference of the thermal expansion coefficients between molding compound and silicon dies is mitigated.

[0066] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the disclosure. Therefore, the scope of the present disclosure is subject to the definition of the scope of the appended claims.