A semiconductor device includes an active layer having an active region, a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer and extending along a first direction, and multiple first P-GaN islands disposed on the active region and under the drain electrode. A vertical projection of the drain electrode on the active region covers the entirety of a vertical projection of each of the first P-GaN islands on the active region.

Semiconductor devices including an interspersed gate structure are described. In one example, a semiconductor device comprises a semiconductor substrate including a source region, a gate region, a drain region, and a drain access region, where a heterojunction structure is disposed over the semiconductor substrate. The heterojunction structure includes a buffer layer over the semiconductor substrate and a barrier layer over the buffer layer. A p-doped III-N layer is disposed over the barrier layer in the gate region, where the p-doped III-N layer may contain a concentration profile of an element with one or more peaks at different distances from a surface of the p-doped III-N layer.

Disclosed is a method of manufacturing a semiconductor device including: growing a buffer layer, a channel layer, and a barrier layer on a substrate layer sequentially; forming a gate contact on the barrier layer; forming a first dielectric layer, and a first photoresist layer over the gate contact and the barrier layer sequentially; patterning the first photoresist layer to form a first photoresist mask with a hole pattern; performing a first wet etching, a dry etching, and a second wet etching using the hole pattern to etch the first dielectric layer to form an opening exposing a portion of the gate contact; stripping the first photoresist mask; forming a gate metal layer to cover the first dielectric layer and fill the gate contact opening; patterning the gate metal layer to form a gate electrode connected to the gate contact and a gate field plate connected to the gate electrode.

Disclosed is a structure including a substrate and a transistor on the substrate. The transistor includes a barrier layer above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate and a secondary gate. The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions on the barrier layer positioned laterally adjacent to opposing sidewalls, respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion on the top surface of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the structure.

A high electron mobility transistor (HEMT) device including a substrate and a semiconductor stack is provided. The semiconductor stack comprises a lower channel layer, an insertion layer (ISL) positioned above the lower channel layer for confining electrons in the lower channel layer, an upper channel layer, an interface enhancement layer (IEL) positioned above the upper channel layer for confining the electrons in the upper channel layer, and a barrier layer positioned above the IEL. The ISL and the IEL are formed above the lower channel layer and the upper channel layer respectively to create a first and second wide bandgap heterojunction. The ISL and the IEL each provides a higher energy band with a potential barrier with respect to the electrons generated between the ISL and the lower channel layer, and between the IEL and the upper channel layer. The potential barrier prevents or reduces a flow of hot electrons.