An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.

A vertical-conduction MOSFET device formed in a body of silicon carbide having a first and a second face and a peripheral zone. A drain region, of a first conductivity type, extends in the body between the two faces. A body region, of a second conductivity type, extends in the body from the first face, and a source region, having the first conductivity type, extends to the inside of the body region from the first face of the body. An insulated gate region extends on the first face of the body and comprises a gate conductive region. An annular connection region, of conductive material, is formed within a surface edge structure extending on the first face of the body, in the peripheral zone. The gate conductive region and the annular connection region are formed by a silicon layer and by a metal silicide layer overlying the silicon layer.

A semiconductor memory device includes a semiconductor substrate that includes first, second, and third regions spaced apart from each other in a first direction on a well region; first and second conductive layers that are spaced apart in the first direction; a first contact connected to the first region and passing through a first opening through the first conductive layer; a second contact connected to the third region and passing through a second opening through the second conductive layer; and third and fourth conductive layers that are between the first and second conductive layers and are spaced apart from each other in the first direction. The first conductive layer and the first contact are connected to each other to be at substantially the same potential, and the second conductive layer and the second contact are connected to each other to be at substantially the same potential.

A method for manufacturing a semiconductor device includes forming a device isolation layer in a substrate to define an active region, forming a gate insulating layer covering at least a portion of the active region, forming a gate electrode on the gate insulating layer, and forming an interlayer insulating layer on the gate electrode. The gate insulating layer includes a first portion overlapping with the active region and a second portion overlapping with the device isolation layer. The forming of the gate insulating layer includes etching at least a part of the second portion of the gate insulating layer to thin the part of the second portion of the gate insulating layer.

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation).

A semiconductor device includes a stressed substrate stressed by a first stress, a first stressed channel formed in the substrate and having the first stress, and a first strained gate electrode strained by a first strain generating element. A first strained gate electrode is formed over the first stressed channel, the first strained gate electrode including a first lattice-mismatched layer to induce a second stress to the first stressed channel.

Various embodiments provide memory devices and methods for forming the same. A substrate is provided, the substrate having one or more adjacent memory cells formed thereon. Each memory cell includes a gate structure, a control gate layer, and a first mask layer. A portion of the control gate layer is removed, to reduce a size of an exposed portion of the control gate layer in a direction parallel to a surface of the substrate. An electrical contact layer is formed on an exposed sidewall of the control gate layer and an exposed surface of the substrate. A barrier layer is formed on a sidewall of the memory cell. A conductive structure is formed on the substrate. The conductive structure has a significantly larger distance from control gate layer than from the gate structure, and the barrier layer forms an isolation layer between the conductive structure and the control gate layer.

Provided is a technique of securing reliability of a gate insulating film, as much as in a Si power MOSFET, in a semiconductor device in which a semiconductor material having a larger band gap than silicon is used, and which is typified by, for example, an SiC power MOSFET. In order to achieve this object, in the in the SiC power MOSFET, the gate electrode GE is formed in contact with the gate insulating film GOX, and is formed of the polycrystalline silicon film PF1 having the thickness equal to or smaller than 200 nm, and the polycrystalline silicon film PF2 formed in contact with the polycrystalline silicon film PF1, and having any thickness.

A semiconductor device formed on a semiconductor substrate having a substrate top surface, comprising: a gate trench extending from the substrate top surface into the semiconductor substrate; a gate electrode in the gate trench; a gate top dielectric material disposed over the gate electrode; a body region adjacent to the gate trench; a source region embedded in the body region; a metal layer disposed over at least a portion of a gate trench opening and at least a portion of the source region, wherein: the source region has a curved sidewall portion that is adjacent to the gate trench, and that extends above the gate top dielectric material.