A semiconductor structure and a method of forming the same are provided. In an embodiment, a semiconductor structure includes a first plurality of channel members over a backside dielectric layer, a second plurality of channel members over the backside dielectric layer, a silicide feature disposed in the backside dielectric layer, and a source/drain feature disposed over the silicide feature and extending between the first plurality of channel members and the second plurality of channel members. The silicide feature extends through an entire depth of the backside dielectric layer.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

A device includes a first gate structure, a first gate spacer and a second gate spacer, a first lightly doped drain region, a first drain region, a first protection layer, and a first drain silicide region. The first gate structure is over a substrate. The first gate spacer and a second gate spacer are on opposite sides of the first gate structure, respectively. The first lightly doped drain region laterally extends from directly below the first gate spacer to past an outermost sidewall of the first gate spacer. The first drain region laterally extends from the first lightly doped drain region in a direction away from the first gate structure. The first protection layer is over the first lightly doped drain region. The first drain silicide region is over the first drain region and contacts an end surface of the first protection layer.

A semiconductor device includes a substrate, a metal gate and a poly gate. The substrate includes a first region and a second region. The metal gate is disposed on the first region of the substrate. The poly gate is disposed on the second region of the substrate. A gate area of the poly gate is greater than that of the metal gate.

A position of an upper surface of a lead-out portion of a gate electrode is higher than an upper surface of an active portion of the gate electrode. An insulating film has a first raised portion positioned on a side surface of the active portion of the gate electrode via a sidewall spacer and a second raised portion positioned on a side surface of the lead-out portion of the gate electrode via the sidewall spacer. An active portion of a field plate electrode is in contact with the first raised portion, and a position of an uppermost portion of the lead-out portion of the field plate electrode is lower than a position of an uppermost portion of the insulating film positioned over the upper surface of the lead-out portion of the gate electrode.

A semiconductor device includes an active area on a substrate, a gate insulating layer on the active area, and a gate electrode structure on the gate insulating layer. The gate electrode structure includes a first blocking impurity-doped layer in contact with an upper surface of the gate insulating layer and doped with a blocking impurity, a middle layer on the first blocking impurity-doped layer, and a second blocking impurity-doped layer on the middle layer and doped with the blocking impurity. A blocking impurity concentration in the second blocking impurity-doped layer is higher than a blocking impurity concentration in the first blocking impurity-doped layer.

Device structures and fabrication methods for MOSFETs having a novel multiple-conductive layer T-shaped gate (as viewed in cross-section). The novel T-gate significantly decreases the gate resistance R.sub.G of a MOSFET device and thus increases the figure-of-merit f.sub.MAX (the maximum device oscillation frequency, or the frequency at which the maximum power gain equals unity) and reduces the noise factor (NF) of the device. Fabrication of the novel MOSFET devices may be readily integrated into existing IC fabrication processes, and such MOSFETs may have gate lengths L.sub.g scaled below the lithographic capabilities of the fabrication process. Some embodiments include conformal gate side-spacers. Some embodiments include non-conformal air-gapped gate side-spacers that result in reduced parasitic gate-to-source capacitance C.sub.GS and gate-to-drain capacitance C.sub.GD, with concomitant improved performance at high radio frequencies (RF). Embodiments of the novel MOSFET device enable RF circuits, such as low-noise amplifiers (LNAs), to exhibit a better noise figure parameter, NFmin.

A system and method for growing fine grain polysilicon. In one example, the method of forming an integrated circuit includes forming a dielectric layer over a semiconductor substrate, and forming a polysilicon layer over the dielectric layer. The polysilicon layer is formed by a chemical vapor deposition process that includes providing a gas flow including disilane and hydrogen gas over the semiconductor substrate.

The present disclosure relates to a method for fabricating a semiconductor structure. The method includes providing a substrate with a gate structure, an insulating structure over the gate structure, and a S/D region; depositing a titanium silicide layer over the S/D region with a first chemical vapor deposition (CVD) process. The first CVD process includes a first hydrogen gas flow. The method also includes depositing a titanium nitride layer over the insulating structure with a second CVD process. The second CVD process includes a second hydrogen gas flow. The first and second CVD processes are performed in a single reaction chamber and a flow rate of the first hydrogen gas flow is higher than a flow rate of the second hydrogen gas flow.

Structures that include field-effect transistors and methods of forming such structures. The structure comprises a substrate, a dielectric layer on the substrate, a first field-effect transistor including a first semiconductor layer over the dielectric layer and a first gate electrode, and a second field-effect transistor including a second semiconductor layer over the dielectric layer and a second gate electrode adjacent to the first gate electrode. The second semiconductor layer is connected to the first semiconductor layer, and the first and second semiconductor layers are positioned between the first gate electrode and the second gate electrode.