A semiconductor device includes: an IGBT section including a vertical IGBT; and a diode section arranged along the IGBT section and including a diode. The diode section includes a hole injection reduction layer having a first conductivity type and arranged in an upper layer portion of a drift layer, extending to a depth deeper than an anode region constituted by a second conductivity type region in the diode section, having an impurity concentration lower than an impurity concentration of the anode region and higher than an impurity concentration of the drift layer.

According to an embodiment a semiconductor device includes a semiconductor body with a mesa section that may include a rectifying structure and a first drift zone section. The mesa section surrounds a field electrode structure that includes a field electrode and a field dielectric sandwiched between the field electrode and the semiconductor body. A maximum horizontal extension of the field electrode in a measure plane parallel to a first surface of the semiconductor body is at most 500 nm.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a gate electrode, a first source electrode, a second source electrode, and a drain electrode. The second nitride-based semiconductor layer includes a drift region doped, a first barrier region, and a second barrier region. The first and second barrier regions extend downward from a top surface of the second nitride-based semiconductor layer and are separated from each other by a portion of the drift region. The gate electrode is disposed on the first barrier region. The first source electrode is disposed on the portion of the drift region. The second source electrode is disposed on the second barrier region and is electrically coupled with the first source electrode. The drain electrode is connected to the first nitride-based semiconductor layer.

A semiconductor device is provided in which a front surface of an SiC substrate is treated before epitaxial growth so as to reduce crystal defects such as stacking faults. In an aspect, an epitaxial layer is deposited on an SiC substrate in which a periodic texture is formed in a direction perpendicular to a <1100> direction of the SiC substrate and in which an angle between a basal plane of the SiC substrate and a surface of the formed texture is smaller than an off angle.

Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a method for forming a semiconductor device includes forming a first epitaxial layer on sidewalls of trenches and forming second epitaxial layer on the first epitaxial layer where charges in the doped regions along the sidewalls of the first and second trenches achieve charge balance in operation. In another embodiment, the semiconductor device includes a termination structure including an array of termination cells.

An object is to provide a technique that suppresses decrease in the breakdown voltage of a protective element. There is provided a semiconductor device that comprises a vertical MOS transistor and a protective element. A first nitride semiconductor layer has a convex that is protruded toward a second nitride semiconductor layer. The convex has a top face placed at a position to overlap with at least part of an ohmic electrode of a second conductive type when viewed from a stacking direction of a stacked body. The thickness of the second nitride semiconductor layer in a portion which a bottom face of a trench is in contact with is greater than the thickness of the second nitride semiconductor layer in a portion which the top face of the convex is in contact with.

A horizontal MOSFET is arranged in parallel to a horizontal MOSFET and a portion of a return current IL which flows to a linear solenoid flows as a current to the horizontal MOSFET. Therefore, a current which flows to a parasitic transistor is reduced and it is possible to suppress the current which flows to the parasitic transistor provided in the horizontal MOSFET. Since the current which flows to the parasitic transistor is reduced, it is possible to prevent the erroneous operation and breakdown of a semiconductor device forming a synchronous rectification circuit.

Provided is a glass composition for protecting a semiconductor junction which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where a glass material containing lead silicate as a main component is used.

A semiconductor device comprises: a semiconductor layer; and an insulating film that is formed on the semiconductor layer. The insulating film includes an insulating layer that is mainly made of negatively charged microcrystal.

The present disclosure relates to a dielectrically isolated semiconductor device and a method for manufacturing the same. The dielectrically isolated semiconductor device includes a semiconductor substrate, a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, a semiconductor island in the second semiconductor layer, and a first dielectric isolation layer surrounding a bottom and sidewalls of the semiconductor island. The first dielectric isolation layer includes a first portion which is formed from a portion of the first semiconductor layer and extending along the bottom of the semiconductor island, and a second portion which is formed from a portion of the second semiconductor layer and extending along the sidewalls of the semiconductor island. The dielectrically isolated semiconductor devices needs no an SOI wafer and reduces manufacturing cost.