Glass composition for protecting semiconductor junction, method of manufacturing semiconductor device and semiconductor device

Abstract

Provided is a glass composition for protecting a semiconductor junction which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where a glass material containing lead silicate as a main component is used.

Claims

1. A semiconductor device, comprising: a silicon-made semiconductor element having a pn junction; and a glass layer which covers the pn junction, wherein the glass layer is formed by baking a layer made of a glass composition, the glass composition comprises fine glass particles prepared from a material in a molten state obtained by melting a glass material which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, and at least two oxides of alkaline earth metals selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, the content of SiO.sub.2 falls within a range of 49.5 mol % to 58.8 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, the content of the oxides of alkaline earth metals falls within a range of 7.4 mol % to 12.9 mol %, the content of CaO falls within a range of 2.0 mol % to 5.3 mol %, the content of MgO falls within a range of 1.0 mol % to 2.3 mol %, the content of BaO falls within a range of 2.6 mol % to 5.3 mol %, and an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6.

2. The semiconductor device according to claim 1, wherein the average linear expansion coefficient within the temperature range of 50 C. to 550 C. falls within a range of 3.3810.sup.6 to 4.0810.sup.6.

3. The semiconductor device according to claim 1, wherein a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 falls within a range of 65 mol % to 75 mol %.

4. A method of manufacturing a semiconductor device, the method comprising: preparing a silicon-made semiconductor element having a pn junction; and forming a glass layer by baking a layer made of a glass composition such that the glass layer covers the pn junction, wherein the glass composition comprises fine glass particles prepared from a material in a molten state obtained by melting a glass material which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, and at least two oxides of alkaline earth metals selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, the content of SiO.sub.2 falls within a range of 49.5 mol % to 58.8 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, the content of the oxides of alkaline earth metals falls within a range of 7.4 mol % to 12.9 mol %, the content of CaO falls within a range of 2.0 mol % to 5.3 mol %, the content of MgO falls within a range of 1.0 mol % to 2.3 mol %, the content of BaO falls within a range of 2.6 mol % to 5.3 mol %, and an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.13106.

5. The method according to claim 4, wherein said preparing the semiconductor element comprises: preparing a semiconductor base body having the pn junction parallel to a main surface; and forming a trench extending from the main surface of the semiconductor base body to a depth below the pn junction, and said forming the glass layer comprises forming the glass layer covering the pn junction exposed inside the trench.

6. The method according to claim 5, wherein said forming the glass layer comprises forming the glass layer such that the glass layer directly covers the pn junction exposed in the trench.

7. The method according to claim 5, wherein said forming the glass layer comprises forming an insulation layer over the pn junction exposed in the trench, and forming the glass layer such that the glass layer covers the pn junction with the insulation layer interposed therebetween.

8. The method according to claim 4, wherein said preparing the semiconductor element comprises forming the pn junction exposed on a surface of a semiconductor base body, and said forming the glass layer comprises forming the glass layer such that the glass layer covers the pn junction exposed on the surface of the semiconductor base body.

9. The method according to claim 8, wherein said forming the glass layer comprises forming the glass layer such that the glass layer directly covers the pn junction exposed on the surface of the semiconductor base body.

10. The method according to claim 8, wherein said forming the glass layer comprises forming an insulation layer on the pn junction exposed on the surface of the semiconductor base body, and forming the glass layer such that the glass layer covers the pn junction with the insulation layer interposed therebetween.

11. The method according to claim 4, wherein said forming the glass layer comprises baking the layer made of the glass composition without causing crystallization of the glass layer.

12. A semiconductor device, comprising: a silicon-made semiconductor element having a pn junction; and a glass layer which covers the pn junction, wherein the glass layer is formed by baking a layer made of a glass composition, the glass composition comprises fine glass particles prepared from a material in a molten state obtained by melting a glass material which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, and at least two oxides of alkaline earth metals selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, the content of SiO.sub.2 falls within a range of 49.5 mol % to 58.8 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, the content of the oxides of alkaline earth metals falls within a range of 7.4 mol % to 12.9 mol %, out of the oxides of alkaline earth metals, the content of CaO falls within a range of 2.0 mol % to 7.6 mol %, and the content of BaO falls within a range of 3.7 mol % to 5.9 mol %, and an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6.

13. A method of manufacturing a semiconductor device, the method comprising: preparing a silicon-made semiconductor element having a pn junction; and forming a glass layer by baking a layer made of a glass composition such that the glass layer covers the pn junction, wherein the glass composition comprises fine glass particles prepared from a material in a molten state obtained by melting a glass material which contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, and at least two oxides of alkaline earth metals selected from the group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, the content of SiO.sub.2 falls within a range of 49.5 mol % to 58.8 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, the content of the oxides of alkaline earth metals falls within a range of 7.4 mol % to 12.9 mol %, out of the oxides of alkaline earth metals, the content of CaO falls within a range of 2.0 mol % to 7.6 mol %, and the content of BaO falls within a range of 3.7 mol % to 5.9 mol %, and an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A to FIG. 1D are views for explaining a method of manufacturing a semiconductor device according to an embodiment 4.

(2) FIG. 2A to FIG. 2D are views for explaining the method of manufacturing a semiconductor device according to the embodiment 4.

(3) FIG. 3A to FIG. 3C are views for explaining a method of manufacturing a semiconductor device according to an embodiment 5.

(4) FIG. 4A to FIG. 4C are views for explaining the method of manufacturing a semiconductor device according to the embodiment 5.

(5) FIG. 5A to FIG. 5D are views for explaining a method of manufacturing a semiconductor device according to an embodiment 6.

(6) FIG. 6A to FIG. 6D are views for explaining the method of manufacturing a semiconductor device according to the embodiment 6.

(7) FIG. 7A to FIG. 7D are views for explaining a method of manufacturing a semiconductor device according to an embodiment 7.

(8) FIG. 8A to FIG. 8D are views for explaining a method of manufacturing the semiconductor device according to the embodiment 7.

(9) FIG. 9 is a Table showing conditions and results of examples.

(10) FIG. 10A and FIG. 10B are graphs showing one example of a result of measurement of linear expansion coefficients.

(11) FIG. 11A and FIG. 11B are views for explaining bubbles generated in the inside of a glass layer in a preliminary evaluation.

(12) FIG. 12A and FIG. 12B are photographs for explaining bubbles generated in the inside of the glass layer in a subsequent evaluation.

(13) FIG. 13 is a Table showing the compositions at 18 levels and the result of a preliminary evaluation.

(14) FIG. 14A to FIG. 14D are views for explaining a conventional method of manufacturing a semiconductor device.

(15) FIG. 15A to FIG. 15D are views for explaining a conventional method of manufacturing a semiconductor device.

MODE FOR CARRYING OUT THE INVENTION

(16) Hereinafter, a glass composition for protecting a semiconductor junction, a method of manufacturing a semiconductor device and a semiconductor device according to the present invention are explained in conjunction with embodiments shown in the drawings.

Embodiment 1

(17) The embodiment 1 relates to an embodiment of a glass composition for protecting a semiconductor junction.

(18) The glass composition for protecting a semiconductor junction of the embodiment 1 contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, all oxides of alkaline earth metals of CaO, MgO and BaO, and nickel oxide, and substantially contains none of Pb, As, Sb, Li, Na and K. In this case, to contain some specific components means not only the case where the glass composition contains only such specific components but also the case where the glass composition also contains other components which can be usually contained in the glass composition besides such specific components. Further, to substantially contain no specific element means that the glass composition contains no any such a specific element as the specific component, and does not exclude the glass composition in which the above-mentioned specific element is mixed as an impurity in the glass materials which constitute respective components of glass. To substantially contain no specific element also means that the glass composition contains none of oxide of such a specific element, none of nitride of such a specific element or the like.

(19) To be more specific, the content of SiO.sub.2 falls within a range of 49.5 mol % to 64.3 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, the content of the oxide of alkaline earth metal falls within a range of 7.4 mol % to 12.9 mol %, and the content of nickel oxide falls within a range of 0.01 mol % to 2.0 mol %. With respect to the oxides of alkaline earth metals, the content of CaO falls within a range of 2.0 mol % to 5.3 mol %, the content of MgO falls within a range of 1.0 mol % to 2.3 mol %, and the content of BaO falls within a range of 2.6 mol % to 5.3 mol %. A total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 falls within a range of 65 mol % to 75 mol %. An average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6.

(20) According to the glass composition for protecting a semiconductor junction of the embodiment 1, as can be clearly understood from examples described later, a semiconductor device having high breakdown strength can be manufactured by using a glass material which contains no lead in the same manner as the conventional case where a glass material containing lead silicate as a main component is used.

(21) According to the glass composition for protecting a semiconductor junction of the embodiment 1, an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6 so that the glass composition has a linear expansion coefficient close to a linear expansion coefficient of silicon whereby it is possible to make the warping of the wafer during steps extremely small. Accordingly, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an reverse breakdown voltage characteristic can be also manufactured by increasing a thickness of the glass layer.

(22) According to the glass composition for protecting a semiconductor junction of the embodiment 1, the content of SiO.sub.2 falls within a range of 49.5 mol % to 64.3 mol %, the content of B.sub.2O.sub.3 falls within a range of 8.4 mol % to 17.9 mol %, the content of Al.sub.2O.sub.3 falls within a range of 3.7 mol % to 14.8 mol %, the content of ZnO falls within a range of 3.9 mol % to 14.2 mol %, and the content of the oxide of alkaline earth metal falls within a range of 7.4 mol % to 12.9 mol %. Accordingly, it is possible to set an average linear expansion coefficient of the glass composition for protecting a semiconductor junction within a temperature range of 50 C. to 550 C. to a value (3.3310.sup.6 to 4.1310.sup.6, for example) close to a linear expansion coefficient of silicon without causing the crystallization in the process of vitrification. For this reason, it is possible to make the warping of the wafer during steps extremely small and hence, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an excellent reverse breakdown voltage characteristic can be also manufactured by increasing a thickness of the glass layer.

(23) The reason the content of SiO.sub.2 is set to a value which falls within a range of 49.5 mol % to 64.3 mol % is that when the content of SiO.sub.2 is less than 49.5 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered, while when the content of SiO.sub.2 exceeds 64.3 mol %, there exists a tendency that a baking temperature needs to be elevated.

(24) The reason the content of B.sub.2O.sub.3 is set to a value which falls within a range of 8.4 mol % to 17.9 mol % is that when the content of B.sub.2O.sub.3 is less than 8.4 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of B.sub.2O.sub.3 exceeds 17.9 mol %, there is a tendency that an average linear expansion coefficient is increased.

(25) The reason the content of Al.sub.2O.sub.3 is set to a value which falls within a range or 3.7 mol % to 14.8 mol % is that when the content of Al.sub.2O.sub.3 is less than 3.7 mol %, there is a tendency that the glass composition is liable to be crystallized in the process of vitrification, while when the content of Al.sub.2O.sub.3 exceeds 14.8 mol %, there is a tendency that the insulation property is lowered.

(26) The reason the content of ZnO is set to a value which falls within a range of 3.9 mol % to 14.2 mol % is that when the content of ZnO is less than 3.9 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of ZnO exceeds 14.2 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered, and there is also a tendency that the glass composition is liable to be crystallized in the process of vitrification.

(27) The reason the content of oxide of alkaline earth metal is set to a value Which falls within a range of 7.4 mol % to 12.9 mol % is that when the content of oxide of alkaline earth metal is less than 7.4 mol % there is a tendency that a baking temperature needs to be elevated, while when the content of oxide of alkaline earth metal exceeds 12.9 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(28) The reason the content of CaO out of oxides of alkaline earth metals is set to a value which falls within a range of 2.0 mol % to 5.3 mol % is that when the content of CaO is less than 2.0 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of CaO exceeds 5.3 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(29) The reason the content of MgO is set to a value which falls within a range of 1.0 mol % to 2.3 mol % is that when the content of MgO is less than 1.0 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of MgO exceeds 2.3 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(30) The reason the content of BaO is set to a value which falls within a range of 2.6 mol % to 5.3 mol % is that when the content of BaO is less than 2.6 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of BaO exceeds 5.3 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(31) The reason the content of nickel oxide is set to a value which falls within a range of 0.01 mol % to 2.0 mol % is that when the content of nickel oxide is less than 0.01 mol %, there may be a case where it becomes difficult to suppress the generation of bubbles which may be generated from an interface, between a layer made of the glass composition for protecting a semiconductor junction formed by an electrophoresis method and a silicon substrate in the process of baking the layer made of the glass composition for protecting a semiconductor junction, while when the content of nickel oxide exceeds 2.0 mol %, there is a tendency that the glass composition is liable to be crystallized in the process of vitrification.

(32) The reason a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 is set to a value which falls within a range of 65 mol % to 75 mol % is that when the total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 is less than 65 mol %, there is a tendency that a linear expansion coefficient is excessively increased, while when the total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 exceeds 75 mol %, there is a tendency that the glass composition is liable to be crystallized in the process of vitrification.

(33) The glass composition for protecting a semiconductor junction of the embodiment 1 can be manufactured as folios. That is, raw materials (SiO.sub.2, H.sub.3BO.sub.3, Al.sub.2O.sub.3, ZnO, CaCO.sub.3, MgO, BaCO.sub.3 and NiO) are prepared at the above-mentioned composition ratio (molar ratio), these raw materials are sufficiently mixed and stirred together by a mixer and, thereafter, the mixed raw material is put into a platinum crucible, a temperature of the mixed raw material is elevated up to a predetermined temperature (1550 C. for example) in an electric furnace and is melted for a predetermined time. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. Thereafter, the glass flakes are pulverized by a ball mill or the like until the glass flakes obtain a predetermined average particle size thus manufacturing the powdery glass composition.

Embodiment 2

(34) The embodiment 2 relates to a glass composition for protecting a semiconductor junction.

(35) The glass composition for protecting a semiconductor junction of the embodiment 2 contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO, at least two oxides of alkaline earth metals (CaO and BaO) and nickel oxide, and substantially contains none of Pb, As, Sb, Li, Na and K. In this case, to contain some specific components means not only the case where the glass composition contains only such specific components but also the case where the glass composition also contains other components which can be usually contained in the glass composition besides such specific components. Further, to substantially contain no specific element means that the glass composition contains no any such a specific element as the specific component, and does not exclude the glass composition in which the above-mentioned specific element is mixed as an impurity in the raw materials which constitute respective components or glass. To substantially contain no specific element means that the glass composition contains none of oxide of such a specific element, none of nitride of such a specific element or the like.

(36) In this embodiment, the content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.2, the content of ZnO, the content of oxide of alkaline earth metal, the content of nickel oxide and a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 are substantially equal to the contents of the corresponding compositions of the glass composition for protecting a semiconductor junction of the embodiment 1 In the same manner as the glass composition for protecting a semiconductor junction of the embodiment 1, an average linear expansion coefficient of the glass composition at a temperature of 50 C. to 550 C. also falls within a range of 3.3310.sup.6 to 4.1310.sup.6. Out of oxides of alkaline earth metals, the content of CaO falls within a range of 2.0 mol % to 7.6 mol %, and the content of BaO falls within a range of 3.7 mol % to 5.9 mol %.

(37) In this manner, the glass composition for protecting a semiconductor junction of the embodiment 2 differs from the glass composition for protecting a semiconductor junction of the embodiment 1 with respect to a point that the glass composition contains CaO and BaO as oxides of alkaline earth metals. However, as can be clearly understood from examples described later, a semiconductor device having high breakdown strength can be manufactured by using the glass material which contains no lead in the same manner as the conventional case where a glass material containing lead silicate as a main component is used.

(38) According to the glass composition for protecting a semiconductor junction of the embodiment 2, an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6 so that the glass composition has a linear expansion coefficient close to a linear expansion coefficient of silicon whereby it is possible to make the warping of the wafer during steps extremely small. Accordingly, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an excellent reverse breakdown voltage characteristic can be also manufactured by increasing a thickness of the glass layer.

(39) According to the glass composition for protecting a semiconductor junction of the embodiment 2, the content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.3, the content of ZnO, the content of oxide of alkaline earth metal and the content of nickel oxide are equal to the corresponding contents of the components in the glass composition for protecting a semiconductor junction of the embodiment 1. Accordingly, it is possible to set an average linear expansion coefficient of the glass composition for protecting a semiconductor junction within a temperature range of 50 C. to 550 C. to a linear expansion coefficient (3.3310.sup.6 to 4.1310.sup.6, for example) close to a linear expansion coefficient of silicon without causing the crystallization in the process of vitrification. For this reason, it is possible to make the warping of the wafer during steps extremely small. As a result, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an excellent reverse breakdown voltage characteristic can be also manufactured by increasing a thickness of the glass layer.

(40) The reason the content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.3, the content of ZnO, the content of oxide of alkaline earth metal and the content of nickel oxide of the glass composition for protecting a semiconductor junction of the embodiment 2 are set to values which fall within the above-mentioned ranges is substantially equal to the reason the corresponding contents of the components in the glass composition for protecting a semiconductor junction of the embodiment 1 are set.

(41) The reason the content of CaO out of oxides of alkaline earth metals is set to a value which falls within a range of 2.0 mol % to 7.6 mol % is that when the content of CaO is less than 2.0 mol %, there is a tendency that a baking temperature needs to be elevated, while when the content of CaO exceeds 7.6 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(42) The reason the content of BaO is set to a value which falls within a range of 3.7 mol % to 5.9 mol % is that when the content of BaO is less than 3.7 mol %, there exists a tendency that a baking temperature needs to be elevated, while when the content of BaO, exceeds 5.9 mol %, there may be a case where the resistance to chemicals is lowered or the insulation property is lowered.

(43) The glass composition for protecting a semiconductor junction of the embodiment 2 can be manufactured as follows. That is raw materials (SiO.sub.2, H.sub.2BO.sub.3, Al.sub.2O.sub.3, ZnO, BaCO.sub.3, and NiO) are prepared at the above-mentioned composition ratio (molar ratio), these raw materials are sufficiently mixed and stirred together by a mixer and, thereafter, the mixed raw material is put into a platinum crucible, a temperature of the mixed raw material is elevated up to a predetermined temperature (1550 C., for example) in an electric furnace and is melted for a predetermined time. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. Thereafter, the glass flakes are pulverized by a ball mill or the like until the glass flakes obtain a predetermined average particle size thus manufacturing the powdery glass composition.

Embodiment 3

(44) The embodiment 3 relates to a glass composition for protecting a semiconductor junction.

(45) The glass composition for protecting a semiconductor junction of the embodiment 3 basically contains the substantially same components as the glass composition for protecting a semiconductor junction of the embodiment 1. However, the glass composition for protecting a semiconductor junction of the embodiment 3 differs from the glass composition for protecting a semiconductor junction of the embodiment 1 with respect to a point that the glass composition for protecting a semiconductor junction of the embodiment 3 contains no nickel oxide. That is, the glass composition for protecting a semiconductor junction of the embodiment 3 contains at least SiO.sub.2, B.sub.2O.sub.3, Al.sub.2O.sub.3, ZnO and all oxides of alkaline earth metals of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K. In this case, to contain some specific components means not only the case where the glass composition contains only such specific components but also the case where the glass composition also contains other components which can be usually contained in the glass composition besides such specific components. Further, to substantially contain no specific element means that the glass composition contains no any such a specific element as the specific component, and does not exclude the glass composition in which the above-mentioned specific element is mixed as an impurity in the raw materials which constitute respective components of glass. To substantially contain no specific element means that the glass composition contains none of oxide of such a specific element, none of nitride of such a specific element or the like.

(46) The content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.3, the content of ZnO, the content of oxide of alkaline earth metal, the content of CaO, the content of MgO, the content of BaO and a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 of the glass composition for protecting a semiconductor junction of the embodiment 3 are equal to the contents the corresponding compositions of the glass composition for protecting a semiconductor junction of the embodiment 1. An average linear expansion coefficient of the glass composition of the embodiment 3 at a temperature of 50 C. to 550 C. also falls within a range of 3.310.sup.6 to 4.1310.sup.6 in the same manner as the glass composition for protecting a semiconductor junction of the embodiment 1.

(47) According to the glass composition for protecting a semiconductor junction of the embodiment 3, in the same manner as the glass composition for protecting a semiconductor junction of the embodiment 1, a semiconductor device having high breakdown strength can be manufactured by using a glass material which contains no lead in the same manner as the conventional case where a glass material containing lead silicate as a main component is used.

(48) According to the glass composition for protecting a semiconductor junction of the embodiment 3, an average linear expansion coefficient within a temperature range of 50 C. to 550 C. falls within a range of 3.3310.sup.6 to 4.1310.sup.6 so that the glass composition has a linear expansion coefficient close to a linear expansion coefficient of silicon whereby it is possible to make the warping of the wafer during steps extremely small. Accordingly, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an excellent reverse breakdown voltage characteristic can be manufactured by increasing a thickness of the glass layer.

(49) According to the glass composition for protecting a semiconductor junction of the embodiment 3, the content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.3, the content of ZnO, and the content of oxide of alkaline earth metal are equal to the contents of the corresponding components of the glass composition for protecting a semiconductor junction of the embodiment 1. Accordingly, it is possible to set an average linear expansion coefficient of the glass composition for protecting a semiconductor junction within a temperature range of 50 C. to 550 C. to a value (3.3310.sup.6 to 4.1310.sup.6, for example) close to a linear expansion coefficient of silicon without causing the crystallization in the process of vitrification. For this reason, it is possible to make the warping of the wafer during steps extremely small. As a result, the semiconductor device having an excellent forward breakdown voltage characteristic can be manufactured using a thin wafer, and the semiconductor device having an excellent reverse breakdown voltage characteristic can be also manufactured by increasing a thickness of the glass layer.

(50) The reason the content of SiO.sub.2, the content of B.sub.2O.sub.3, the content of Al.sub.2O.sub.3, the content of ZnO, the content of oxide of alkaline earth metal, the content of CaO, the content of MgO, the content of BaO and a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3 of the glass composition for protecting a semiconductor junction of the embodiment 3 are set to values which fall within the above-mentioned ranges is equal to the reason the contents of the corresponding components of the glass composition for protecting a semiconductor junction of the embodiment 1 are set.

(51) The reason the composition contains no nickel oxide is that even when the composition contains no nickel oxide, there may be a case where it is possible to suppress the generation of bubbles which may be generated from an interface between a layer made of the glass composition for protecting a semiconductor junction formed by an electrophoresis method and a silicon substrate in the process of baking the layer made of the glass composition for protecting a semiconductor junction.

(52) The glass composition for protecting a semiconductor junction of the embodiment 3 can be manufactured as follows. That is, raw materials (SiO.sub.2, H.sub.3BO.sub.3, Al.sub.2O.sub.3, ZnO, CaCO.sub.3, MgO and BaCO.sub.3) are prepared at the above-mentioned composition ratio (molar ratio), these raw materials are sufficiently mixed and stirred together by a mixer and, thereafter, the mixed raw material is put into a platinum crucible, a temperature of the mixed raw material is elevated up to a predetermined temperature (1550 C., for example) in an electric furnace and is melted for a predetermined time. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. Thereafter, the glass flakes are pulverized by a ball mill or the like until the glass flakes obtain a predetermined average particle size thus manufacturing the powdery glass composition.

Embodiment 4

(53) The embodiment 4 relates to a method of manufacturing a semiconductor device.

(54) The method of manufacturing a semiconductor device of the embodiment 4 includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; and a second step of forming a glass layer such that the glass layer covers the pn junction exposure portion. In the second step, the glass layer is formed using the glass composition for protecting a semiconductor junction of the embodiment 1. The first step includes a step of preparing a semiconductor base body in which a pn junction arranged parallel to a main surface of the semiconductor base body is formed; and a step of forming trenches having a depth exceeding the pn junction from one surface of a semiconductor base body thus forming a pn junction exposure portion in the trenches, and the second step includes a step of forming the glass layer such that the glass layer directly covers the pn junction exposure portion in the inside of the trench.

(55) FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D are views for explaining the method of manufacturing a semiconductor device of the embodiment 4. FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D are views showing respective steps of the method of manufacturing a semiconductor device.

(56) In the method of manufacturing a semiconductor device of the embodiment 4, as shown in FIG. 1A to FIG. 1D and FIG. 2A to FIG. 2D, semiconductor base body forming step, trench forming step, glass layer forming step, photoresist forming step, oxide film removing step, roughened surface region forming step, electrode forming step, and semiconductor base body cutting step are performed in this order. Hereinafter, the method of manufacturing a semiconductor device of the embodiment 4 is explained in the order of these steps.

(57) (a) Semiconductor Base Body Forming Step

(58) Firstly, a p.sup.+ diffusion layer 112 is formed by diffusion of a p type impurity from one surface of an n.sup. type semiconductor substrate (n.sup. type silicon substrate) 110, and an n.sup.+ type diffusion layer 114 is formed by diffusion of an n type impurity from the other surface of the n.sup. type semiconductor substrate 110 thus forming a semiconductor base body in which a pn junction arranged parallel to a main surface of the semiconductor base body is formed. Thereafter, oxide films 116, 118 are formed by thermal oxidation on a surface of the p.sup.+ type diffusion layer 112 and a surface of the n.sup.+ type diffusion layer 114 respectively (see FIG. 1A).

(59) (b) Trench Forming Step

(60) Next, predetermined opening portions are formed on the oxide film 116 at predetermined positions by photo etching. After etching the oxide film, subsequently, the semiconductor base body is etched thus forming trenches 120 having a depth exceeding the pn junction from one surface of the semiconductor base body (see FIG. 1B). Along with such formation of the trenches, a pn junction exposure portion A is formed on inner surfaces of the trenches.

(61) (c) Glass Layer Forming Step

(62) Next, a layer made of the glass composition for protecting a semiconductor junction of the embodiment 1 is formed on inner surfaces of the trenches 120 and a surface of the semiconductor base body in the vicinity of the trenches 120 by an electrophoresis method, and the layer made of the glass composition for protecting a semiconductor junction is baked so that a glass layer 124 for passivation is formed on surfaces of the trenches 120 (see FIG. 1C). Accordingly, the pn junction exposure portion in the inside of the trench 120 is brought into a state where the pn junction exposure portion is directly covered with the glass layer 124.

(63) (d) Photoresist Forming Step

(64) Next, a photoresist 126 is formed such that the photoresist 126 covers a surface of the glass layer 124 (see FIG. 1D).

(65) (e) Oxide Film Removing Step

(66) Next, the oxide film 116 is etched using the photoresist 126 as a mask so that the oxide films 116, 118 at a position 130 where an Ni plating electrode film is to be formed are removed (see FIG. 2A).

(67) (f) Roughened Surface Region Forming Step

(68) Next, a surface of the semiconductor base body at the position 130 where the Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 132 for enhancing adhesiveness between the Ni plating electrode and toe semiconductor base body (see FIG. 2B).

(69) (g) Electrode Forming Step

(70) Next, Ni plating is applied to the semiconductor base body thus forming an anode electrode 134 on the roughened surface region 132 and forming a cathode electrode 136 on the other surface of the semiconductor base body (see FIG. 2C).

(71) (h) Semiconductor Base Body Cutting Step

(72) Next, the semiconductor base body is cut by dicing or the like at a center portion of the glass layer 124 thus dividing the semiconductor base body into chips whereby mesa-type semiconductor devices (pn diodes) are manufactured (see FIG. 2D).

(73) Through the above-mentioned steps, the mesa-type semiconductor device having high breakdown strength (semiconductor device of the embodiment 4) 100 can be manufactured.

Embodiment 5

(74) The embodiment 5 relates to a method of manufacturing a semiconductor device.

(75) In the same manner as the method of manufacturing a semiconductor device of the embodiment 4, the method of manufacturing a semiconductor device of the embodiment 5 includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; and a second step of forming a glass layer such that the glass layer covers the pn junction exposure portion. In the second step, the glass layer is formed by using the glass composition for protecting a semiconductor junction of the embodiment 1. However, different from the method of manufacturing a semiconductor device of the embodiment 4, in the method of manufacturing a semiconductor device of the embodiment 5, the first step includes a step of forming the pn junction exposure portion on a surface of the semiconductor base body, and the second step includes a step of forming the glass layer such that the glass layer directly covers the pn junction exposure portion on the surface of the semiconductor base body.

(76) FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C are views for explaining a method of manufacturing a semiconductor device of the embodiment 5. That is, FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C are views showing respective steps of the method of manufacturing a semiconductor device.

(77) In the method of manufacturing the semiconductor device of the embodiment 5, as shown in FIG. 3A to FIG. 3C and FIG. 4A to FIG. 4C, semiconductor base body preparing step, p.sup.+ type diffusion layer forming step, n.sup.+ type diffusion layer forming step, glass layer forming step, glass layer etching step, electrode forming step and semiconductor base body cutting step are performed in this order. Hereinafter, the method of manufacturing a semiconductor device of the embodiment 5 is explained in the order of these steps.

(78) (a) Semiconductor Base Body Preparing Step

(79) Firstly, a semiconductor base body where an n.sup. type epitaxial layer 212 is laminated on an n.sup.+ type silicon substrate 210 is prepared (see FIG. 3A).

(80) (b) p.sup.+ Type Diffusion Layer Forming Step

(81) Next, after forming a mask M1 on the n.sup. type epitaxial layer 212, a p type impurity (boron ion, for example) is injected into a predetermined region on a surface of the n.sup. type epitaxial layer 212 by an ion implantation method using the mask M1. Then, a p.sup.+ type diffusion layer 214 is formed by thermal diffusion (see FIG. 3B).

(82) (c) n.sup.+ Type Diffusion Layer Forming Step

(83) Next, the mask M1 is removed from the n.sup. type epitaxial layer 212 and a mask M2 is formed on the n.sup. type epitaxial layer 212. Thereafter, an n type impurity (arsenic ion, for example) is injected into a predetermined region on the surface of the n.sup. type epitaxial layer 212 by an ion implantation method using the mask M2. Then, an n.sup.+ type diffusion layer 216 is formed by thermal diffusion (see FIG. 3C).

(84) (d) Glass Layer Forming Step

(85) Next, the mask M2 is removed from the n.sup. type epitaxial layer 212. Thereafter, a layer made of the glass composition for protecting a semiconductor junction of the embodiment 1 is formed on the surface of the n.sup. type epitaxial layer 212 by a spin coating method and, then, the layer made of the glass composition for protecting a semiconductor junction is baked thus forming a glass layer 215 for passivation (see FIG. 4A).

(86) (e) Glass Layer Etching Step

(87) Next, a mask M3 is formed on a surface of the glass layer 215 and, thereafter, the glass layer 215 is etched (see FIG. 4B). Due to such etching, a glass layer 217 is formed on a predetermined region on the surface of the n.sup. type epitaxial layer 212.

(88) (f) Electrode forming step

(89) Next, the mask M3 is removed from the surface of the glass layer 217 and, thereafter, an anode electrode 218 is formed on a region of the surface of the semiconductor base body surrounded by the glass layer 217, and a cathode electrode 220 is formed on a back surface of the semiconductor base body (see FIG. 4C).

(90) (g) Semiconductor Base Body Cutting Step

(91) Next, the semiconductor base body is cut by dicing or the like thus dividing the semiconductor base body into chips whereby semiconductor devices (planar-type pn diodes) 200 are manufactured (not shown in the drawing).

(92) Through the above-mentioned steps, planar-type semiconductor device having high breakdown strength (the semiconductor device of the embodiment 5) 200 can be manufactured.

Embodiment 6

(93) In the same manner as the method of manufacturing a semiconductor device of the embodiment 4, the method of manufacturing a semiconductor device of the embodiment 6 includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; and a second step of forming a glass layer such that the glass layer covers the pn junction exposure portion. In the second step, the glass layer is formed using the glass composition for protecting a semiconductor junction of the embodiment 1. However, different from the method of manufacturing a semiconductor device of the embodiment 4, in the method of manufacturing a semiconductor device of the embodiment 6, the second step includes: a step of forming an insulation layer on the pn junction exposure portion in the trench; and a step of forming the glass layer such that the glass layer covers the pn junction exposure portion with the insulation layer interposed therebetween. In the method of manufacturing a semiconductor device of the embodiment 6, a mesa-type pn diode is manufactured as the semiconductor device.

(94) FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6D are views for explaining the method of manufacturing a semiconductor device of the embodiment 6. FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6D are views showing respective steps of the method of manufacturing a semiconductor device.

(95) In the method of manufacturing a semiconductor device of the embodiment 6, as shown in FIG. 5A to FIG. 5D and FIG. 6A to FIG. 6D, semiconductor base body forming step, trench forming step, insulation layer forming step, glass layer forming step, photoresist forming step, oxide film removing step, roughened surface region forming step, electrode forming step, and semiconductor base body cutting step are performed in this order. Hereinafter, the method of manufacturing a semiconductor device of the embodiment 6 is explained in the order of these steps.

(96) (a) Semiconductor Base Body Forming Step

(97) Firstly, a p diffusion layer 112 is formed by diffusion of a p type impurity from one surface of an n.sup. type semiconductor substrate (n.sup. type silicon substrate) 110, and an n.sup.+ type diffusion layer 114 is formed by diffusion of an n type impurity from the other surface of the n.sup. type semiconductor substrate 110 thus forming a semiconductor base body in which a pn junction arranged parallel to a main surface of the semiconductor base body is formed. Thereafter, oxide films 116, 118 are formed by thermal oxidation on a surface of the p.sup.+ type diffusion layer 112 and a surface of the n.sup.+ type diffusion layer 114 respectively (see FIG. 5A).

(98) (b) Trench Forming Step

(99) Next, predetermined opening portions are formed on the oxide film 116 at predetermined positions by photo etching. After etching the oxide film, subsequently, the semiconductor base body is etched thus forming trenches 120 having a depth exceeding the pn junction from one surface of the semiconductor base body (see FIG. 5B). Along with such formation of the trenches, a pn junction exposure portion A is formed on an inner surfaces of the trench.

(100) (c) Insulation Layer Forming Step

(101) Next, an insulation layer 121 formed of a silicon oxide film is formed on inner surfaces of the trenches 120 by a thermal oxidation method using dry oxygen (DryO.sub.2) (see FIG. 5C). A thickness of the insulation layer 121 is set to a value which falls within a range of 5 nm to 60 nm (20 nm, for example). The insulation layer is formed such that a semiconductor base body is introduced into a diffusion furnace, and, thereafter, thermal oxidation treatment is performed at a temperature of 900 C. for 10 minutes while supplying an oxygen gas into the diffusion furnace. When the thickness of the insulation layer 121 is less than 5 nm, there may be a case where a reverse current reduction effect cannot be acquired. On the other hand, when the thickness of the insulation layer 121 exceeds 60 nm, there may be a case where a layer made of a glass composition cannot be formed by an electrophoresis method in a next glass layer forming step.

(102) (d) Glass Layer Forming Step

(103) Next, a layer made of the glass composition for protecting a semiconductor junction of the embodiment 1 is formed on inner surfaces of the trenches 120 and a surface of the semiconductor base body in the vicinity of the trenches 120 by an electrophoresis method and, then, the layer made of the glass composition for protecting a semiconductor junction is baked thus forming a glass layer 124 for passivation (see FIG. 5D). in forming the layer made of the glass composition for protecting a semiconductor junction on the inner surfaces of the trenches 120, the layer made of the glass composition for protecting a semiconductor junction is formed such that the layer made of the glass composition for protecting a semiconductor junction covers the inner surfaces of the trenches 120 with an insulation layer 121 interposed therebetween. Accordingly, the pn junction exposure portion A in the trench 120 is brought into a state where the pn junction exposure portion A is covered with the glass layer 124 with the insulation layer 121 interposed therebetween.

(104) (e) Oxide Film Removing Step

(105) Next, a photoresist 126 is formed such that the photoresist 126 covers the surface of the glass layer 124 and, thereafter, the oxide film 116 is etched using the photoresist 126 as a mask so that the oxide film 116 formed at a position 130 where an Ni plating electrode film is to be formed is removed (see FIG. 6A).

(106) (f) Roughened Surface Region Forming Step

(107) Next, a surface of the semiconductor base body at the position 130 where the Ni-plating electrode film is to be formed is subjected to surface roughening treatment thus forming a roughened surface region 132 for enhancing adhesiveness between an Ni plating electrode and the semiconductor base body (see FIG. 6B).

(108) (g) Electrode Forming Step

(109) Next, Ni plating is applied to the semiconductor base body thus forming an anode electrode 134 on the roughened surface region 132 and forming a cathode electrode 136 on the other surface of the semiconductor base body (see FIG. 6C).

(110) (h) Semiconductor Base Body Cutting Step

(111) Next, the semiconductor base body is cut by dicing or the like at a center portion of each glass layer 124 thus dividing the semiconductor base body into chips whereby semiconductor devices (mesa-type pn diodes) 102 are manufactured (see FIG. 6D).

(112) Through the above-mentioned steps, the mesa-type semiconductor device having high breakdown strength (semiconductor device of the embodiment 6) 102 can be manufactured.

Embodiment 7

(113) In the same manner as the method of manufacturing a semiconductor device, of the embodiment 5, the method of manufacturing a semiconductor device of the embodiment 7 includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion where a pn junction is exposed; and a second step of forming a glass layer such that the glass layer covers the pn junction exposure portion. In the second step, the glass layer is formed using the glass composition for protecting a semiconductor junction of the embodiment 1. However, different from the method of manufacturing a semiconductor device of the embodiment 5, in the method of manufacturing a semiconductor device of the embodiment 7, the second step includes: a step of forming an insulation layer on the pn junction exposure portion on a surface of a semiconductor base body; and a step of forming the glass layer such that the glass layer covers the pn junction exposure portion with the insulation layer interposed therebetween. In the method of manufacturing a semiconductor device of the embodiment 7, a planar-type pn diode is manufactured as the semiconductor device.

(114) FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D are views for explaining the method of manufacturing a semiconductor device of the embodiment 7. FIG. 7A to FIG. 8A to FIG. 8D are views showing respective steps or the method of manufacturing a semiconductor device.

(115) In the method of manufacturing a semiconductor device of the embodiment 7, as shown in FIG. 7A to FIG. 7D and FIG. 8A to FIG. 8D, semiconductor base body preparing step, p.sup.+ type diffusion layer forming step, n.sup.+ type diffusion layer forming step, insulation layer forming step, glass layer forming step, etching step, electrode forming step and semiconductor base body cutting step are performed in this order. Hereinafter, the method of manufacturing a semiconductor device of the embodiment 7 is explained in the order of these steps.

(116) (a) Semiconductor Base Body Preparing Step

(117) Firstly, a semiconductor base body where an n.sup. type epitaxial layer 212 is laminated on an n.sup.+ type silicon substrate 210 is prepared (see FIG. 7A).

(118) (b) p.sup.+ Type Diffusion Layer Forming Step

(119) Next, after forming a mask M1 on the n.sup. type epitaxial layer 212, a p type impurity (boron ion, for example) is injected into a predetermined region on a surface of the n.sup. type epitaxial layer 212 by an ion implantation method using the mask M1. Then, a p.sup.+ type diffusion layer 214 is formed by thermal diffusion (see FIG. 1B).

(120) (c) n.sup.+ Type Diffusion Layer Forming Step

(121) Next, the mask M1 is removed from the n.sup. type epitaxial layer 212 and a mask M2 is formed on the n.sup. type epitaxial layer 212. Thereafter, an n type impurity (arsenic ion, for example) is injected into a predetermined region on the surface of the n.sup. type epitaxial layer 212 by an ion implantation method using the mask M2. Then, an n.sup.+ type diffusion layer 216 is formed by thermal diffusion (see FIG. 7C). In this step, a pn junction exposure portion A is formed on a surface of the semiconductor base body.

(122) (d) Insulation Layer Forming Step

(123) Next, the mask M2 is removed from the n.sup. type epitaxial layer 212. Thereafter, an insulation layer 218 formed of a silicon oxide film is formed on the surface of the n.sup. type epitaxial layer 212 (and on a back surface of the n.sup.+ type silicon substrate 210) by a thermal oxidation method using dry oxygen (DryO.sub.2) (see FIG. 7D). A thickness of the insulation layer 218 is set to a value which falls within a range of 5 nm to 60 nm (20 nm, for example). The insulation layer 218 is formed such that a semiconductor base body is introduced into a diffusion furnace and, thereafter, thermal oxidation treatment is applied to the semiconductor base body at a temperature of 900 C. for 10 minutes while supplying an oxygen gas into the diffusion furnace. When the thickness of the insulation layer 218 is less than 5 nm, there may be a case where a reverse current reduction effect cannot be acquired. On the other hand, when the thickness of the insulation layer 218 exceeds 60 nm, there may be a case where a layer made of the glass composition cannot be formed by an electrophoresis method in the next glass layer forming step.

(124) (e) Glass Layer Forming Step

(125) Next, a layer made of the glass composition for protecting a semiconductor junction of the embodiment 1 is formed on a surface of the insulation layer 218 by an electrophoresis method and, then, the layer made of the glass composition for protecting a semiconductor junction is baked thus forming a glass layer 220 for passivation (see FIG. 8A).

(126) (f) Etching Step

(127) Next, after forming a mask M3 on the surface of the glass layer 220, the glass layer 220 is etched (see FIG. 8B). Subsequently, the insulation layer 218 is etched (see FIG. 8C). Due to such etching, the insulation layer 218 and the glass layer 220 are formed on a predetermined region on the surface of the n.sup. type epitaxial layer 212.

(128) (g) Electrode Forming Step

(129) Next, the mask M3 is removed from the surface of the glass layer 220 and, thereafter, an anode electrode 222 is formed on a region of the surface of the semiconductor base body surrounded by the glass layer 220, and a cathode electrode 224 is formed on a back surface of the semiconductor base body (see FIG. 8D).

(130) (h) Semiconductor Base Body Cutting Step

(131) Next, the semiconductor base body is cut by dicing or the like thus dividing the semiconductor base body into chips whereby the semiconductor devices (planar-type pn diodes) 202 are manufactured (not shown in the drawing).

(132) Through the above-mentioned steps, a planar-type semiconductor device having high breakdown strength (the semiconductor device of the embodiment 7) 202 can be manufactured.

EXAMPLES

(133) 1. Preparation of Specimens

(134) FIG. 9 is a Table showing conditions and results of examples. Raw materials are prepared at composition ratios indicated in examples 1 to 8 and comparison examples 1 and 2 (see FIG. 9). These raw materials are sufficiently mixed and stirred together by a mixer and, thereafter, the mixed raw material is put into a platinum crucible, a temperature of the mixed raw material is elevated up to a predetermined temperature (1350 C. to 1550 C., for example) in an electric furnace and is melted for two hours. Then, the material in a molten state is made to flow out from the crucible and is fed to water-cooled rolls so that glass flakes in a flaky shape are obtained. The glass flakes are pulverized by a ball mill until the glass flakes obtain an average particle size of 5 m thus obtaining powdery glass composition.

(135) The raw materials used in the examples are SiO.sub.2, Al.sub.2O.sub.3, ZnO, CaCO.sub.3, MgO, BaCO.sub.3, NiO, ZrO.sub.2 and PbO.

(136) 2. Evaluation

(137) The respective glass compositions obtained by the above-mentioned methods are evaluated in accordance with the following evaluation aspects.

(138) (1) Evaluation Aspect 1 (Environmental Burden)

(139) The object of the present invention lies in that a semiconductor device having high breakdown strength can be manufactured by using a glass material which contains no lead in the same manner as the conventional case where a glass material containing lead silicate as a main component is used and hence, the score good is given when the glass composition contains no lead component, and the score bad is given when the glass composition contains a lead component.

(140) (2) Evaluation Aspect 2 (Baking Temperature)

(141) When the baking temperature is excessively high, the baking temperature largely influences a semiconductor device in a manufacturing process. Accordingly, the score good is given when the baking temperature is equal to or below 900 C., and the score bad is given when the baking temperature exceeds 900 C.

(142) (3) Evaluation Aspect 3 (Resistance to Chemicals)

(143) The score good is given when the glass composition exhibits insolubility with respect to both aqua regia and plating liquid, and the score bad is given when the glass composition exhibits solubility to at least one of aqua regia and plating liquid.

(144) (4) Evaluation Aspect 4 (Average Linear Expansion Coefficient)

(145) Glass plates in a flaky shape are prepared from a material in a molten state obtained in the above-mentioned 1. Preparation of specimens, and an average linear expansion coefficient of the glass composition at a temperature of 50 C. to 550 C. is measured by using the glass plates in a flaky shape. The average linear expansion coefficient is measured by a total expansion measuring method (temperature elevation speed: 10 C./min) using Thermomechanical Analyzers TMA-60 made by SHIMADZU CORP where silicon single crystal having a length of 20 mm is used as a standard specimen.

(146) FIG. 10A and FIG. 10B are graphs showing one example of the result of measurement of an average linear expansion coefficient, wherein FIG. 10A is a graph showing the measurement result of the glass composition for protecting a semiconductor junction according to the example 3, and FIG. 10B is a graph showing the measurement result of the glass composition for protecting a semiconductor junction according to the comparison example 1. The score good is given when a difference between the average linear expansion coefficient of the glass composition at a temperature of 50 C. to 550 C. and a linear expansion coefficient (3.7310.sup.6) of silicon is 0.410.sup.6 or less, and the score bad is given when the difference exceeds 0.410.sup.6 In the column of the evaluation aspect 4 in FIG. 9, numerals in parentheses indicate average linear expansion coefficient of the glass composition within a temperature range of 50 C. to 550 C.10.sup.6.

(147) (5) Evaluation Aspect 5 (Insulation Property)

(148) A semiconductor device (pn diodes) is manufactured by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 4 or 6, and a reverse breakdown voltage characteristic of a semiconductor device manufactured by the method is measured. In examples 7 and 8 and comparison examples 1 and 2, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 4. In examples 1 to 6, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 6. As the result of the measurement, the score good is given when a reverse breakdown voltage characteristic of a semiconductor device falls within a normal range, and the score bad is given when a reverse breakdown voltage characteristic of a semiconductor device falls outside a normal range.

(149) (6) Evaluation Aspect 6 (Presence or Non-Presence of Crystallization)

(150) A semiconductor device (pn diodes) is manufactured by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 4 or 6. In the examples 7 and 8 and the comparison examples 1 and 2, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 4. In the examples 1 to 6, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 6. As the result, the score good is given when vitrification can be performed without causing the crystallization in the process of vitrification of a layer made of the glass composition, and the score bad is given when vitrification cannot be performed due to the crystallization.

(151) (7) Evaluation Aspect 7 (Presence or Non-Presence of Generation of Bubbles)

(152) A semiconductor device (pn codes) is manufactured by a method substantially equal to the method of manufacturing a semiconductor device of the embodiment 4 or 6, and the observation is made whether or not bubbles are generated in the inside of the glass layer 124 (particularly, in the vicinity of an interface between the glass layer 124 and the silicon substrate) in the course of vitrification (preliminary evaluation). Further, the glass compositions for protecting a semiconductor junction according to the examples 1 to 6 and the comparison examples 1 and 2 are applied to silicon substrates each having a size of 10 mm10 mm by coating respectively thus forming layers made of the glass composition for protecting a semiconductor junction on the silicon substrates, and the layers made of the glass composition for protecting a semiconductor junction are baked thus forming glass layers. Then, the observation is made whether or not bubbles are generated in the inside of the glass layers (particularly, in the vicinity of an interface between the glass layer and the semiconductor base body) (subsequent evaluation) In the examples 7 and 8 and the comparison examples 1 and 2, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 4. In the examples 1 to 6, a semiconductor device is manufactured by the method of manufacturing a semiconductor device of the embodiment 6.

(153) FIG. 11A and FIG. 11B are views for explaining bubbles b generated in the inside of the glass layer 124 in the preliminary evaluation. FIG. 11A is a cross-sectional view of a semiconductor device where no bubbles b are generated, while FIG. 11B is a cross-sectional view of a semiconductor device where bubbles b are generated. FIG. 12A and FIG. 12B are photographs for explaining bubbles b generated in the inside of the glass layer 124 in the subsequent evaluation. FIG. 12A is a photograph showing an interface between the silicon substrate and the glass layer where no bubbles b are generated in an enlarged manner, and FIG. 12B is a photograph showing an interface between the silicon substrate and the glass layer where bubbles b are generated in an enlarged manner. As the result of the experiment, it is found that there is enough correlation between the result of the preliminary evaluation of the present invention and the result of the subsequent evaluation of the present invention. In the subsequent evaluation, the score good is given when no bubbles having a diameter of 50 m or more are generated in the inside of the glass layer, the score fair is given when one to twenty bubbles having a diameter of 50 m or more are generated in the inside of the glass layer, and the score bad is given when twenty one or more bubbles having a diameter of 50 m or more are generated in the inside, of the glass layer.

(154) (8) Comprehensive Evaluation

(155) The score good is given when the score good is given with respect to all of the above-mentioned evaluation aspects 1 to 7, and the score bad is given when the score fair or bad is given with respect to at least one of the respective evaluation aspects.

(156) 3. Evaluation Result

(157) As can be understood also from FIG. 9, in all glass compositions according to the comparison examples 1 and 2, the score bad is given with respect to at least one of the evaluation aspects so that the score bad is given with respect to the comprehensive evaluation. That is, in the glass compositions according to the comparison example 1, the score bad is given with respect to the evaluation aspects 1 and 4. Further, in the glass composition according to the comparison example 2, the score bad is given with respect to the evaluation aspects 3 and 4.

(158) To the contrary, in all glass compositions according to the examples 1 to 8, the score good is given with respect to all evaluation aspects (evaluation aspects 1 to 7). As the result, it is found that, although all glass compositions according to the examples 1 to 8 are a glass material which contains no lead, these glass compositions satisfy all the following conditions (a) to (d), that is, the condition (a) that the glass composition can be baked at a proper temperature (for example, 900 C. or below), the condition (b) that the glass composition withstands chemicals used in steps, the condition (c) that the glass composition has a linear expansion coefficient close to a linear expansion coefficient of silicon (particularly an average linear expansion coefficient at a temperature of 50 C. to 550 C. being close to a Linear expansion coefficient of silicon), and the condition (d) that the glass composition has excellent insulation property. It is also found that these glass compositions satisfy the condition (e) that the glass composition is not crystallized in the process of vitrification, and the condition (f) that the occurrence of a state that a reverse breakdown voltage characteristic of the semiconductor device is deteriorated can be suppressed by suppressing the generation of bubbles which may be generated from an interface between the glass layer and the silicon substrate in the process of forming the glass layer.

(159) From other experiments which the inventors carried out, it is also found that the semiconductor devices according to the examples 1 to 6 are the semiconductor devices which exhibit a low reverse current irrespective of the composition of the glass layer or a baking condition of the glass layer compared to the semiconductor devices according to the examples 7 and 8.

(160) Also from other experiments which the inventors carried out, it is also found that bubbles are hardly generated from an interface between the silicon substrate and the glass layer in the process of forming the glass layer by baking the layer made of the glass composition in the semiconductor devices according to the examples 1 to 6 compared to the semiconductor devices according to the examples 7 and 8.

(161) Also from other experiments which the inventors carried out, it is found that when a resin-sealed semiconductor device is manufactured by molding a semiconductor device according to the examples 1 to 8 with a resin, such a resin-sealed semiconductor device exhibits higher resistance to a reverse bias at a high temperature than a resin-sealed semiconductor device which is manufactured by molding a semiconductor device according to the comparison example 1 with a resin.

(162) [Preliminary Evaluation]

(163) In deciding the composition of the above-mentioned examples 1 to 8, the preliminary evaluation is carried out at 18 levels, and the result of the preliminary experiment is used as the reference. FIG. 13 is a Table showing the compositions at 18 levels and the result of the preliminary evaluation. The following matters (1) to (4) can be understood from FIG. 13.

(164) (1) From a viewpoint of difficulty in crystallization in the process of vitrification, the smaller a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3, the more difficult the crystallization becomes. The larger the content of Al.sub.2O.sub.3, the more difficult the crystallization becomes. The smaller the content of ZnO, the more difficult the crystallization becomes. The larger the content of oxide of alkaline earth metal, the more difficult the crystallization becomes.

(165) (2) From a viewpoint of an average linear expansion coefficient within a temperature range of 50 C. to 550 C., the followings tendencies are found. That is, the larger a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3, the smaller the average linear expansion coefficient becomes. The larger the content of Al.sub.2O.sub.3, the smaller the average linear expansion coefficient becomes. With respect to ZnO, it is found that there is a tendency that the larger the content of ZnO, the smaller the average linear expansion coefficient becomes. However, such a tendency is brought about by the decrease of the average Linear expansion coefficient caused by the crystallization and hence, it is considered desirable to set the content of ZnO small from a viewpoint of vitrification.

(166) (3) From a viewpoint of a glass transition temperature Tg, the followings tendencies are found. That is, the smaller a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3, the lower the glass transition temperature Tg becomes. The larger a ratio of the content of B.sub.2O.sub.3 with respect to the content of SiO.sub.2, the lower the glass transition temperature Tg becomes. The smaller the content of Al.sub.2O.sub.3, the lower the glass transition temperature Tg becomes. The larger the content of ZnO, the lower the glass transition temperature Tg becomes.

(167) (4) From a viewpoint of a yield point (softening point) Ts, the followings tendencies are found. That is, the smaller a total content of the content of SiO.sub.2 and the content of B.sub.2O.sub.3, the lower the yield point Ts becomes. The larger a ratio of the content of B.sub.2O.sub.3 with respect to the content of SiO.sub.2, the lower the yield point Ts becomes. The larger the content of BaO, the lower the yield point Ts becomes.

(168) Although the glass composition for protecting a semiconductor junction, the method of manufacturing a semiconductor device and such a semiconductor device according to the present invention have been explained heretofore in conjunction with the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and can be carried out without departing from the gist of the present invention. For example, the following modifications are conceivable.

(169) (1) In the above-mentioned embodiment 3, the glass composition for protecting a semiconductor junction of the present invention has been explained by using the glass composition which basically has the substantially same composition as the glass composition for protecting a semiconductor junction of the embodiment 1 as a base and contains no nickel oxide. However, the present invention is not limited to such glass composition. For example, the present invention also includes the glass composition for protecting a semiconductor junction which basically has the substantially same composition as the glass composition for protecting a semiconductor junction of the embodiment 2 as a base and contains no nickel oxide.

(170) (2) In the above-mentioned embodiments 1 and 2, although nickel oxide is used as at least one metal oxide selected from a group consisting of nickel oxide, copper oxide, manganese oxide and zirconium oxide (metal oxide having property of suppressing the generation of bubbles in the process of vitrification), the present invention is not limited to nickel oxide. For example, in place of nickel oxide, copper oxide, manganese oxide or zirconium oxide may be used.

(171) Although the present invention relates to the glass composition for protecting a semiconductor junction which substantially contains none of Pb, As, Sb, Li, Na and K, the present invention also includes the glass composition for protecting a semiconductor junction which substantially contains none of Pb, P, As, Sb, Li, Na and K.

(172) (4) In the above-mentioned embodiments 4 to 7, although the glass layer is formed using the glass composition for protecting a semiconductor junction of the embodiment 1, the present invention is not limited to such glass composition. For example, the glass layer may be formed using the glass composition for protecting a semiconductor junction of the embodiment 2 or 3. Further, the glass layer may be formed using other glass compositions for protecting a semiconductor junction which fall within the scope of claim 1 or 3.

(173) (5) In the above-mentioned respective embodiments, the present invention has been explained by taking diodes (mesa-type pn diode, planar-type pn diode) as an example. However, the present invention is not limited to such diodes. The present invention is also applicable to all types of semiconductor devices where a pn junction is exposed (for example, thyristor, power MOSFET, IGBT and the like).