A semiconductor device includes: a substrate having a first region and a second region; a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; a first bump on the first region; a first doped layer on the first fin-shaped structure and the bump; and a gate structure covering the bump.

A semiconductor device includes a first substrate doped with an impurity of a first conductivity-type, a first well region formed in the first substrate and doped with an impurity of a second conductivity-type, different from the first conductivity-type, a first guard band that extends in a first direction, parallel to an upper surface of the substrate, is in the first well region, and doped with an impurity of the second conductivity-type, a second guard band facing the first guard band, in the substrate, and doped with an impurity of the first conductivity-type, a first electrode structure electrically connected to the first guard band, a second electrode structure electrically connected to the second guard band, and a first insulating layer on sidewalls of the first electrode structure and the second electrode structure, the first electrode structure, the insulating layer, and the second electrode structure provide a capacitor.

A semiconductor structure includes a substrate, a first power device and a second power device in the substrate, at least one isolation feature between the first and second power device, and a trapping feature adjoining the at least one isolation feature in the substrate.

A semiconductor device includes a first active region including at least one first recess; a second active region including at least one second recess; an isolation region including a diffusion barrier that laterally surrounds at least any one active region of the first active region and the second active region; a first recess gate filled in the first recess; and a second recess gate filled in the second recess, wherein the diffusion barrier contacts ends of at least any one of the first recess gate and the second recess gate.

An integrated circuit includes an active device formed in a semiconductor layer of a first conductivity type, a first guard ring of the first conductivity type formed in the semiconductor layer surrounding at least part of the active device; a second guard ring of the second conductivity type formed in the semiconductor layer surrounding the first guard ring and the active device and including comprising alternating first well regions of the first conductivity type and the second well regions of the second conductivity type, the first and second well regions being electrically shorted together and electrically coupled to a ground potential or floating; and a third guard ring of the first conductivity type formed in the semiconductor layer surrounding the second guard ring. The first and third guard rings do not receive direct electrical connection.

A semiconductor device including an insulating film in a first region of a semiconductor substrate; a first impurity region and a second impurity region of a first conductivity type, each of the regions including a part located deeper than the insulating film in contact with each other, and the insulating film being sandwiched by the first and second impurity regions in planar view in the first region of the semiconductor substrate; a metal silicide film on the first impurity region and in Schottky junction with the first impurity region; a first impurity of the first impurity region having a peak of a concentration profile deeper than a bottom of the insulating film; a second impurity of the second impurity region having a concentration higher than a concentration of the first impurity in a part of the first impurity region shallower than the bottom of the insulating film.

A semiconductor arrangement and method of formation are provided. A semiconductor arrangement includes a first semiconductor device adjacent a second semiconductor device. The first semiconductor device includes a first gate over a first shallow well in a substrate. A first active area is in the first shallow well on a first side of the first gate. The second semiconductor device includes a second gate over a second shallow well. A third active area is in the second shallow well on a first side of the second gate. The second shallow well abuts the first shallow well in the substrate to form a P-N junction. The P-N junction increases capacitance of the semiconductor arrangement, as compared to a device without such a P-N junction.

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first bump on the first region and a second bump on the second region; forming a first doped layer on the first fin-shaped structure and the first bump; and forming a second doped layer on the second fin-shaped structure and the second bump.

A set of transistor elements includes a substrate of a first doping type and a first well and a second well, both of a second doping type and both formed on the substrate. The set of transistor elements also includes a first complementary transistor cell and a second complementary transistor cell. The set of transistor element also includes an anti-propagation region of the first doping type between the first well and the second well.

A method includes forming fin semiconductor features on a substrate. A dopant-containing dielectric material layer is formed on sidewalls of the fin semiconductor features and the substrate. A precise material modification (PMM) process is performed to the dopant-containing dielectric material layer. The PMM process includes forming a first dielectric material layer over the dopant-containing dielectric material layer; performing a tilted ion implantation to the first dielectric material layer so that a top portion of the first dielectric material layer is doped to have a modified etch characteristic different from an etch characteristic of a bottom portion of the first dielectric material layer; and performing an etch process to selectively remove the top portion of the first dielectric material layer and the top portion of the dopant-containing dielectric material layer.