Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

In the present invention, there is provided a semiconductor device including: element isolation regions formed in a state of being buried in a semiconductor substrate such that an element formation region of the semiconductor substrate is interposed between the element isolation regions; a gate electrode formed on the element formation region with an gate insulating film interposed between the gate electrode and the element formation region, the gate electrode being formed so as to cross the element formation region; and source-drain regions formed in the element formation region on both sides of the gate electrode, wherein a channel region made of the element formation region under the gate electrode is formed so as to project from the element isolation regions, and the source-drain regions are formed to a position deeper than surfaces of the element isolation regions.

Embodiments of the present disclosure are directed to co-integrating multiple fin heights with bottom dielectric isolations for effective width tuning. In a non-limiting embodiment, a semiconductor structure includes a first shallow trench isolation (STI) region formed over a first portion of a substrate and a second STI region formed over a second portion of the substrate. A topmost surface of the second STI region is coplanar to a topmost surface of the first STI region. A first fin is formed in the first STI region and a second fin is formed in the second STI region. A topmost surface of the second fin is coplanar to a topmost surface of the first fin. A bottom dielectric isolation (BDI) region is positioned between the first fin and the substrate, thereby providing a first effective width and a second effective width for the first fin and second fin, respectively.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first isolation structure over a first end of a fin. A gate structure is over the fin and is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end. The second isolation structure is spaced apart from the gate structure. The first isolation structure and the second isolation structure both comprise a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material. The recessed second dielectric material laterally surrounds at least a portion of a third dielectric material different from the first and second dielectric materials.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

A packaged multichip isolation device includes leadframe including a first and second die pad, with a first and second lead extending outside a molded body having a downward extending lead bend near their outer ends. A first integrated circuit (IC) die on the first die pad has a first bond pad connected to the first lead that realizes a transmitter or receiver. A second IC die on the second die pad has a second bond pad connected to the second lead that realizes another of the transmitter and receiver. An isolation component is in a signal path of the isolation device including a capacitive isolator, or inductors for transformer isolation on or between the die. A midpoint of the thickness of the die pad is raised above a top level of the leads and in an opposite vertical direction relative to the downward extending bend of the external leads.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.

A semiconductor structure and a method for forming the same are provided. The method includes forming a first protruding structure and a second protruding structure over a substrate, and forming a first insulation material layer on the first protruding structure and the second protruding structure. The method includes performing a pre-treatment process on the first insulation material layer to form a first treated insulation material layer, and forming a second insulation material layer on the first treated insulation material layer. The method includes performing a first insulation material conversion process on the first treated insulation material layer and the second insulation material layer. The first protruding structure and the second protruding structure are bent toward opposite directions during the first insulation material conversion process.

A semiconductor device includes first to third electrodes, a semiconductor part, a control electrode and an insulating body. The second electrode is opposite to the first electrode. The semiconductor part is provided between the first electrode and the second electrode. The semiconductor part includes first and second trenches next to each other in a front side facing the second electrode. The second trench has a first width in a first direction directed from the first trench toward the second trench. The third electrode and the control electrode are provided inside the first trench. Another third electrode and the insulating body is provided inside the second trench. The insulating body is positioned in the second trench between said another third electrode and the second electrode. The insulating body has a second width in the first direction. The second width is equal to the first width of the second trench.

A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.