Devices providing tensile/compressive stressor layers for gate-all-around devices. A first GAA device and a second GAA are disposed having a shallow trench isolation feature and one of more stressor layers between gate structures of the first GAA device and the second GAA. The stressor layers can provide tensile stress to a channel layer of the first GAA device and a compressive stress to another channel layer of the second GAA device.

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

Semiconductor channel layers vertically aligned and stacked one on top of another, each separated by a gate stack material, a source-drain epitaxy region adjacent to the semiconductor channel layers, a vertical side surface of the source-drain epitaxy region is adjacent to a vertical side surface of a conductive trench contact. A first set and a second set of semiconductor channel layers, a conductive trench contact between them and a source-drain between the first set and the conductive trench contact. Forming a first stack, a second stack and a third stack of nanosheet layers, forming a first, second and third sacrificial gate, forming a first source drain between the first and second stack, forming a second source drain between the second and third, forming a vertical trench in the first source drain while protecting the second source drain, and forming a stressor material layer in the vertical trench.

Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.

According to one embodiment, a semiconductor device includes a first element isolating area, a first element area surrounding the first element isolating area, a second element isolating area surrounding the first element area a first gate electrode provided on and across the first element isolating area, the first element area, and the second element isolating area, and a second gate electrode isolated from the first gate electrode and provided on and across the first element isolating area, the first element area, and the second element isolating area.

A method includes etching a semiconductor substrate to form a trench and a semiconductor strip. A sidewall of the semiconductor strip is exposed to the trench. The method further includes depositing a silicon-containing layer extending into the trench, wherein the silicon-containing layer extends on the sidewall of the semiconductor strip, filling the trench with a dielectric material, wherein the dielectric material is on a sidewall of the silicon-containing layer, and oxidizing the silicon-containing layer to form a liner. The liner comprises oxidized silicon. The liner and the dielectric material form parts of an isolation region. The isolation region is recessed, so that a portion of the semiconductor strip protrudes higher than a top surface of the isolation region and forms a semiconductor fin.

A transistor is provided. The transistor includes a substrate, a gate structure, a semiconductor structure, and a dielectric component. The gate structure is over the substrate and the semiconductor structure is adjacent to the gate structure. The semiconductor structure has a first side facing the gate structure and a second side laterally opposite the first side. The dielectric component is in the substrate. The dielectric component has a first portion adjacent to the second side of the semiconductor structure and a second portion under the first portion, wherein the second portion extends under the gate structure.