In some embodiments, a method for manufacturing forms a semiconductor device, such as a transistor. A dielectric stack is formed on a semiconductor substrate. The stack comprises a plurality of dielectric layers separated by one of a plurality of spacer layers. Each of the plurality of spacer layers is formed of a different material than immediately neighboring layers of the plurality of dielectric layers. A vertically-extending hole is formed through the plurality of dielectric layers and the plurality of spacer layers. The hole is filled by performing an epitaxial deposition, with the material filling the hole forming a wire. The wire is doped and three of the dielectric layers are sequentially removed and replaced with conductive material, thereby forming upper and lower contacts to the wire and a gate between the upper and lower contacts. The wire may function as a channel region for a transistor.

Energy-filtered cold electron devices use electron energy filtering through discrete energy levels of quantum wells or quantum dots that are formed through band bending of tunneling barrier conduction band. These devices can obtain low effective electron temperatures of less than or equal to 45K at room temperature, steep electrical current turn-on/turn-off capabilities with a steepness of less than or equal to 10 mV/decade at room temperature, subthreshold swings of less than or equal to 10 mV/decade at room temperature, and/or supply voltages of less than or equal to 0.1 V.

Disclosed herein are nanoscale devices comprising one or more ferroelectric nanoshells characterized as having an extreme curvature in at least one spatial dimension. Also disclosed are ferroelectric field effect transistors and metal ferroelectric metal capacitors comprising one or more ferroelectric nanoshells. Methods for controlling spontaneous ferroelectric polarization in nanoshell devices are also disclosed.

There is provided a method for fabricating an asymmetric vertical nanowire MOSFET on a semiconductor substrate comprising at least one vertical nanowire, comprising a core portion and a shell portion circumscribing the core portion. The method comprises depositing a protection layer on the semiconductor substrate, forming a top contact around a remaining portion of the vertical nanowire not covered by the protection layer, removing the protection layer, depositing a spacer layer on the semiconductor substrate, removing a shell portion of the intermediate portion of the bottom portion of the vertical nanowire, trimming a shell portion of the upper portion of the bottom portion of the vertical nanowire, depositing a metal gate on the spacer layer, and forming a lower and an upper source drain portions.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

A method of chemically etching, comprising: providing a base layer, the base layer comprising a first section and a second section, the first section comprising a first material, the second section comprising a second material; providing a resist layer, wherein a first portion of the resist layer covers at least a portion of the first section of the base layer, and wherein a second portion of the resist layer covers at least a portion of the second section of the base layer; and exposing the first and second portions of the resist layer to a first chemical etchant, such that the first chemical etchant migrates through the first portion of the resist layer to react with the first material of the first section of the base layer and removes the first portion of the resist layer, and such that the second portion of the resist layer is not removed.

A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.

A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and an epitaxial structure beside the channel structure. The semiconductor device structure also includes a metal gate stack over the semiconductor nanostructures. The metal gate stack includes a gate dielectric layer, a first work function layer over the gate dielectric layer, and a metal oxide layer over the first work function layer. The metal oxide layer is thinner than the first work function layer. The metal gate stack also includes a second work function layer over the metal oxide layer.

The present disclosure describes a semiconductor device having an asymmetric source/drain (S/D) design. The semiconductor device includes multiple semiconductor layers on a substrate, a gate structure wrapped around the multiple semiconductor layers, an inner spacer structure between the multiple semiconductor layers and in contact with a first side of the gate structure, and an epitaxial layer in contact with a second side of the gate structure. The second side is opposite to the first side.