A method includes forming a plurality of channel layers above a (110)-orientated substrate, the channel layers arranged in a <110> direction normal to a top surface the (110)-orientated substrate and extending in a <110> direction perpendicular to the <110> direction; epitaxial growing a plurality of silicon layers on either side of each of the channel layers; doping the silicon layers with boron; epitaxial growing a plurality of first silicon germanium layers on the silicon layers; forming a gate structure surrounding each of the channel layers.

Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric isolation layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric isolation layer has a thickness in a range of from 0 nm to 10 nm.

A semiconductor device includes first and second fins, first and second hafnium oxide layers, first and second cap layers, and first and second metal gate electrodes. The first and second fins protrude above a substrate and respectively have an n-channel region and a p-channel region. The first and second hafnium oxide layers wrap around the n-channel region and the p-channel region, respectively. The first and second cap layers wrap around the first and second annular hafnium oxide layers, respectively. The first and second cap layers are made of a same material that is lanthanum oxide, yttrium oxide, or strontium oxide. The first and second metal gate electrodes wrap around the first and second cap layers, respectively. The first and second metal gate electrodes have a same metal composition. The first and second gate dielectrics have a same dielectric composition.

A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure, and source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers. Each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, the first and third semiconductor layers include silicon (Si), and the second semiconductor layer includes silicon-germanium (SiGe). Side surfaces of the first to third semiconductor layers in the second direction are in contact with the gate structure.