H10D30/402

Quantum dot device

A silicon-based quantum device for confining charge carriers is provided. The device comprises: a substrate having a first planar region 137; a silicon layer 32 which forms part of the substrate and includes a step 33 with an edge 34 and a second planar region 135, wherein the second planar region 135 is substantially parallel to and offset from the first planar region 137; a first electrically insulating layer 42 provided on the silicon layer 32, overlying the step 33; a first metallic layer 51, provided on the first electrically insulating layer 42, overlying the step 33, arranged to be electrically connected such that a first confinement region 10 can be induced in which a charge carrier or charge carriers can be confined at the edge 34; and a second metallic layer 52, provided overlying the second planar region 135 of the silicon layer, wherein the second metallic layer is: electrically separated from the first metallic layer 51; and arranged to be electrically connected such that a second confinement region 11 can be induced in which a charge carrier or charge carriers can be confined only in the second planar region 135 of the silicon layer 32 under the second metallic layer 52, and the first confinement region 10 is couplable to the second confinement region 11; wherein the first confinement region 10 is displaced from the second confinement region 11 in a direction that is perpendicular to the edge 34. A method of assembling a silicon-based quantum device and a method of using a silicon-based quantum device are also provided.

Charge sensor

A charge sensor according to the present disclosed technology includes a quantum dot to have a first end connected to an input terminal via a first tunnel junction and a second end connected to an output terminal via a second tunnel junction, and an inductor connected in parallel to the quantum dot.

QUANTUM COMPUTATION DEVICE AND OPERATION THEREOF

A method is provided, including: applying a magnetic field according to a two-qubit gate operation performed with a quantum device; transmitting a voltage signal to a gate structure, arranged above first and second quantum dots in the quantum device, to generate a coupling signal that includes a first sine squared wave; and performing, by the magnetic field and the coupling signal, the two-qubit gate operation to the first and second qubits in the first and second quantum dots.

METHOD OF FABRICATING QUANTUM-DOT STRUCTURE THROUGH SELF-ASSEMBLY AND QUANTUM-DOT STRUCTURE

A method of fabricating a quantum-dot structure includes the steps of preparing a semiconductor material layer formed on a substrate; forming an insulating layer from a portion of the semiconductor material layer by oxidizing the semiconductor material layer; and forming quantum dots which are located in the insulating layer and are made of a semiconductor material by diffusing the semiconductor material into the insulating layer by annealing. According to the method of fabricating the quantum-dot structure, it is possible to form the quantum dots made of the semiconductor material from the substrate through self-assembly. According to the method of fabricating the quantum-dot structure, it is possible to form quantum dots and a tunneling structure thereof through self-assembly, and it is possible to fabricate devices such as a single electron transistor based on quantum dots, using processes of existing silicon (Si)-based devices.

Self-aligned gate isolation for multi-directional gate layouts in quantum and semiconductor devices

One embodiment of the invention provides a method for fabricating a self-aligned gate structure comprising forming at least one first trench having a first width and at least one second trench having a second width in a gate structure comprising a first metallic gate layer. The first width is smaller than the second width. The method comprises depositing at least one conformal dielectric layer on the first metallic gate layer. The dielectric layer completely fills the first trench and partially fills the second trench, such that a portion of the second trench is unfilled. The method comprises depositing a conformal second metallic gate layer on the dielectric layer. The second metallic gate layer fills the unfilled portion of the second trench. The method comprises removing portions of the second metallic gate layer to expose the dielectric layer. Remaining portions of the second metallic gate layer include self-aligned metallic gate electrodes.

METHOD FOR MANUFACTURING SILICON SUBSTRATE FOR QUANTUM COMPUTER, SILICON SUBSTRATE FOR QUANTUM COMPUTER, AND SEMICONDUCTOR APPARATUS

A method for manufacturing a silicon substrate for a quantum computer, the method includes the steps of forming a Si epitaxial layer by epitaxial growth using a Si source gas as a silicon-based raw material gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on a silicon substrate, forming an oxygen (O) -doped layer by oxidizing a surface of the Si epitaxial layer, and forming a Si epitaxial layer by epitaxial growth using a Si source gas, in which a total content of 28Si and 30Si in a whole silicon contained in the silicon-based raw material gas is 99.9% or more, on the -doped layer.

Semiconductor device and associated manufacturing method

A semiconductor device includes a substrate; a plurality of gate stacks situated horizontally following one another on the substrate, each gate stack including a layer of a dielectric material in contact with the substrate and a layer of a conductive material on the layer of dielectric material; a source and a drain situated on the substrate on either side of the plurality of gate stacks; a plurality of first spacers made of a first dielectric material, called secondary spacers, having a first width, called width of the secondary spacers, the source and the drain being separated from the closest gate stack by a secondary spacer; at least one main spacer made of a second dielectric material, a main spacer being situated between each gate stack, the width of the main spacer(s) being greater than the width of the secondary spacers.

Quantum processing element and system

The present disclosure provides a quantum processing device comprising: one or more functional nanowires, each functional nanowire connected to at least one of a source and a drain; a sensing nanowire spaced from the one or more functional nanowires and connected to at least one of a source and a drain; one or more gate electrodes capacitively coupled with each of the one or more functional nanowires; one or more electrodes capacitively coupled with the sensing nanowire; and a floating coupler positioned between and electrostatically coupling the one or more functional nanowires and the sensing nanowire; and a controller connected to the one or more gates of the sensing nanowire and the one or more gates of the one or more functional nanowires.

Device with a detection structure with coulomb blockade superimposed on a quantum dot

A quantum device formed from a substrate, the substrate being covered with a semiconductor region forming a quantum dot, and a detection structure with a Coulomb blockade for detecting a state of charge of the quantum dot, the detection structure with the Coulomb blockade including a detection island disposed above and facing the quantum dot and coupled to the quantum dot by electrostatic coupling, the detection structure further including a first tunnel junction between the detection island and a first gate block, the first gate block being juxtaposed with the detection island.