Patent classifications
H10D86/80
Semiconductor on insulator substrate with back bias
A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.
Power storage element, manufacturing method thereof, and power storage device
Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.
Display device and electronic apparatus
A display panel including pixels disposed on a substrate, where each of the pixels includes a light emitting element, and a capacitor. The capacitor of a first one of the pixels is partially overlapped, in a vertical direction, by respective pixel areas of two of the pixels. The anode of the capacitor of the first one of the pixels may be disposed closer to the substrate than a cathode of the capacitor, thereby reducing a parasitic capacitance between the capacitor and an anode of the light emitting element of one of the two pixels overlapping the capacitor.
INTEGRATION OF A REPLICA CIRCUIT AND A TRANSFORMER ABOVE A DIELECTRIC SUBSTRATE
A method includes forming a replica circuit above a surface of a glass-type material. The replica circuit includes a thin-film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The method further includes forming a transformer above the surface of the glass-type material. The transformer is coupled to the replica circuit, and the transformer is configured to facilitate an impedance match between the replica circuit and an antenna.
ESD-PROTECTIVE-FUNCTION-EQUIPPED COMPOSITE ELECTRONIC COMPONENT
An ESD-protective-function-equipped composite electronic component is provided that includes multiple Zener diodes formed from first and second semiconductor layers. Moreover, the second semiconductor layers are disposed on an insulating substrate and in the same plane. The electronic component includes electrodes extending from each of the Zener diodes and one or more thin-film circuit element connected in series between a pair of the electrodes.
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
Integration of a replica circuit and a transformer above a dielectric substrate
A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna.
Display device and method of manufacturing the same
A display device includes: a first wiring line and a second wiring line separated from each other on a substrate; a gate insulating layer on the first wiring line and the second wiring line; a step difference compensation pattern between the first wiring line and the second wiring line on the gate insulating layer; a protective layer on the step difference compensation pattern; and a pixel electrode on the protective layer.
SEMICONDUCTOR ON INSULATOR SUBSTRATE WITH BACK BIAS
A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.
PLANAR NANO-OSCILLATOR ARRAY HAVING PHASE LOCKING FUNCTION
Provided is a planar nano-oscillator array having phase locking function, including two or more planar nano-oscillators which are arranged in parallel. The two oscillators are connected by planar resistors and capacitors, and a structure thereof includes: electrodes; respectively introducing two pairs of laterally arranged parallel insulation notch grooves into two-dimensional electron gas layers, so as to form oscillation channels; vertically disposing separating insulation notch grooves, so that a planar resistor A with low resistance which is connected to the electrode is formed on the left side, and a planar resistor B with low resistance which is connected to the electrode is formed on the right side; and arranging, between the two oscillators, an insulation capacitor notch groove which is parallel to the oscillation channels, insulating materials having a high dielectric constant being filled therein.