The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.

The present application relates to a silicon-on-insulator transverse device and a manufacturing method therefor. The device comprises: a substrate; a buried dielectric layer provided on the substrate; a drift region provided on the buried dielectric layer, a vertical conductive structure extending downwards from the drift region to the buried dielectric layer; a low-K dielectric provided in the buried dielectric layer and surrounding the bottom of the vertical conductive structure; and a dielectric layer provided on a side surface of the vertical conductive structure and located between the vertical conductive structure and the drift region and above the low-K dielectric.

An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.

An integrated circuit structure including a metal-insulator-metal (MIM) capacitor module and a thin-film resistor (TFR) module is provided. The MIM capacitor module includes a bottom electrode base formed in a lower metal layer, a bottom electrode formed in a dielectric region between the lower metal layer and an upper metal layer, an insulator formed over the bottom electrode, and a top electrode formed in the upper metal layer over the insulator. The bottom electrode includes a cup-shaped bottom electrode component and a bottom electrode fill component formed in an interior opening defined by the cup-shaped bottom electrode component. The TFR module includes a pair of metal heads formed in the dielectric region and a resistor element connected across the pair of metal heads. Each metal head includes a cup-shaped head component and a head fill component formed in an interior opening defined by the cup-shaped head component.

A semiconductor device having a novel structure is provided. The semiconductor device includes a first element layer including a first memory cell, a second element layer including a second memory cell, and a silicon substrate including a driver circuit. The first element layer is provided between the silicon substrate and the second element layer. The first memory cell includes a first transistor and a first capacitor. The second memory cell includes a second transistor and a second capacitor. One of a source and a drain of the first transistor and one of a source and a drain of the second transistor are each electrically connected to a wiring for electrical connection to the driver circuit. The wiring is in contact with a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor and is provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate.

An electronic circuit comprises a first resistor and a second resistor. The first resistor comprises: a first sheet (e.g. layer or film) of resistive (i.e. electrically resistive) material; and a first pair of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness of the first sheet. The second resistor comprises: a second sheet (e.g. layer or film) of resistive material; and a second pair of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

An electronic circuit comprises a first resistor and a second resistor. The first resistor comprises: a first sheet (e.g. layer or film) of resistive (i.e. electrically resistive) material; and a first pair of conductive contacts, each arranged in electrical contact with the first sheet, and arranged such that a shortest resistive path in the first sheet between the first pair of contacts passes through the first sheet and has a length equal to a thickness of the first sheet. The second resistor comprises: a second sheet (e.g. layer or film) of resistive material; and a second pair of conductive contacts, each arranged in electrical contact with the second sheet, and arranged such that a shortest resistive path in the second sheet between the second pair of contacts passes along at least a portion of a length of the second sheet.

A switched capacitor power source circuit includes: an integrated circuit for converting an input voltage into a predetermined output voltage by charging and discharging a plurality of capacitance elements via a plurality of switching elements using a plurality of clock signals with different phases. A well layer disposed under each of the capacitance elements is connected via a load circuit to a point of potential equal to or lower than a potential of a semiconductor substrate constituting the integrated circuit.