A neural network device with synapses having memory cells each having a floating gate and a first gate over first and second portions of a channel region disposed between source and drain regions, and a second gate over the floating gate or the source region. First lines each electrically connect the first gates in one of the memory cell columns, second lines each electrically connect the second gates in one of the memory cell rows, third lines each electrically connect the source regions in one of the memory cell rows, and fourth lines each electrically connect the drain regions in one of the memory cell columns. The synapses receive a first plurality of inputs as electrical voltages on the first or fourth lines, and provide a first plurality of outputs as electrical currents on the third lines.

The present application discloses a semiconductor device having a sidewall oxidized dielectric and a method for fabricating the same. The semiconductor device includes a substrate; a tunnel insulating layer disposed over the substrate; a floating gate disposed over the tunnel insulating layer; a laterally oxidized intervention layer disposed over the floating gate; and a control gate disposed over the laterally oxidized intervention layer. The laterally oxidized intervention layer includes a sidewall portion and a center portion, wherein the sidewall portion has an oxygen concentration greater than that of the center portion.

The present application discloses a semiconductor device having a sidewall oxidized dielectric and a method for fabricating the same. The semiconductor device includes a substrate; a tunnel insulating layer disposed over the substrate; a floating gate disposed over the tunnel insulating layer; a laterally oxidized intervention layer disposed over the floating gate; and a control gate disposed over the laterally oxidized intervention layer. The laterally oxidized intervention layer includes a sidewall portion and a center portion, wherein the sidewall portion has an oxygen concentration greater than that of the center portion.

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.

A nonvolatile memory device includes a plurality of cell strings each including a channel layer extending in a first direction, at least one charge tunneling layer adjacent to the channel layer in a second direction intersecting the first direction, a plurality of charge storage layers adjacent to the at least one charge tunneling layer in the second direction, the plurality of charge storage layers spaced apart in the first direction, a plurality of charge blocking layers adjacent to respective charge storage layers of the plurality of charge storage layers in the second direction, a plurality of gate electrodes adjacent to respective charge blocking layers of the plurality of charge blocking layers in the second direction, and a plurality of separation layers configured to isolate the plurality of charge storage layers, the plurality of charge blocking layers, and the plurality of gate electrodes in the first direction.

In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

The present application discloses a semiconductor device having a sidewall oxidized dielectric and a method for fabricating the same. The semiconductor device includes a substrate; a tunnel insulating layer disposed over the substrate; a floating gate disposed over the tunnel insulating layer; a laterally oxidized intervention layer disposed over the floating gate; and a control gate disposed over the laterally oxidized intervention layer. The laterally oxidized intervention layer includes a sidewall portion and a center portion, wherein the sidewall portion has an oxygen concentration greater than that of the center portion.

Structures for a flash memory cell array and methods of forming a structure for a flash memory cell array. The structure comprises a first gate stack including a first control gate and a second gate stack including a second control gate. The first control gate has a first sidewall, a second sidewall opposite from the first sidewall, and a gate strap region, and the gate strap region includes a projection extending outwardly from the first sidewall of the first control gate. The second control gate has a first sidewall and a second sidewall opposite from the first sidewall, and the second sidewall of the second control gate faces the second sidewall of the first control gate.

Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.