A device includes a floating gate, a control gate, and an erase gate and a select gate. The floating gate is over a substrate. The control gate is over the floating gate. The erase gate and the select gate are on opposite sides of the control gate, wherein the floating gate gets wider and then gets narrower in a direction from the control gate toward the substrate.

A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

A method for forming a semiconductor structure is provided. The method includes providing a substrate with active regions, forming a first gate layer on the active regions of the substrate, and conformally forming an inter-gate dielectric layer on the substrate and the first gate layer. The inter-gate dielectric layer forms a first opening between the first gate layer. The method includes forming a second gate layer on the inter-gate dielectric layer, wherein the second gate layer is filled in the first opening, forming a patterned photoresist layer on the second gate layer, and using the patterned photoresist layer as a mask and patterning the second gate layer to form a second opening. The second opening is directly over the first opening. The method further includes patterning the second gate layer, the inter-gate dielectric layer, and the first gate layer to form a word line structure on the substrate.

A semiconductor device includes a stacked gate structure, a plurality of stacks and a first conductive layer. The stacks are disposed aside the stacked gate structure and arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. The first conductive layer is disposed between segmented portions of the stacks along the second direction, wherein top surfaces of the segmented portions of the stacks are higher than a top surface of the first conductive layer.

A device includes an isolation structure, a transistor, and a capacitor. The isolation structure is embedded in a substrate. The transistor is over the substrate and includes a gate structure, a gate dielectric layer between the gate structure and the substrate, and source/drain regions in the substrate. The capacitor is over the substrate and includes a top electrode over the substrate, a bottom electrode in the substrate and in contact with the isolation structure, and an insulating layer between the top electrode and the bottom electrode. A nitrogen concentration of the insulating layer is different from a nitrogen concentration of the gate dielectric layer.

A manufacturing method of a semiconductor device includes the following steps. A substrate is provided. A multilayer over the substrate is formed. The multilayer is patterned, to form a plurality of stacks and a stacked gate structure, the stacks arranged along both a first direction and a second direction perpendicular to the first direction, wherein the stacks are extended continuously along the first direction and segmented in the second direction. A first conductive layer is formed between segmented portions of the stacks along the second direction.

A flash memory device and method of making the same are disclosed. The flash memory device is located on a substrate and includes a floating gate electrode, a tunnel dielectric layer located between the substrate and the floating gate electrode, a smaller length control gate electrode and a control gate dielectric layer located between the floating gate electrode and the smaller length control gate electrode. The length of a major axis of the smaller length control gate electrode is less than a length of a major axis of the floating gate electrode.

In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.

A semiconductor device includes a first source region and a drain region disposed on a substrate; a first gate stack comprising a first floating gate and a first control gate, and disposed between the first source region and the drain region; a first select gate disposed on one sidewall of the first gate stack; a first spacer disposed on a lower sidewall of the first select gate, and disposed adjacent to the first source region; a second spacer disposed on an upper sidewall of the first select gate; a first control gate silicide layer disposed on the first control gate; and a first select gate silicide layer disposed on the first select gate, and disposed between the first spacer and the second spacer.