Provided is a semiconductor device, which prevents unnecessary voltage drop in a MOS transistor that is connected in series in a location between a booster circuit and a memory main body portion, to thereby operate on a low voltage and improve the ON/OFF ratio so that chip size shrinking and memory performance improvement are accomplished simultaneously. In a semiconductor memory device including a memory transistor portion and a select transistor portion, at least the select transistor portion is formed of a fin-shaped single-crystal semiconductor thin film.

A nonvolatile memory device includes a conductive layer, a semiconductor layer extending in a first direction on the conductive layer, a first insulating layer provided between the conductive layer and the semiconductor layer, a word line extending in a second direction on the semiconductor layer, the second direction intersecting the first direction, a charge storage layer provided between the semiconductor layer and the word line, and a circuit electrically connected to the conductive layer. The circuit applies an electric potential to the conductive layer when programming data, the electric potential of the conductive layer having the same polarity as an electric potential of the word line.

According to one embodiment, an inter-electrode insulating film interposed between a floating gate electrode and a control gate electrode includes a lower layer insulating film disposed on a side closer to the floating gate electrode, an upper layer insulating film disposed on a side closer to the control gate electrode, and an intermediate insulating film interposed between the lower layer insulating film and the upper layer insulating film, wherein the intermediate insulating film contains a first element, and the lower layer insulating film contains the first element and a second element, such that a ratio of the first element relative to the second element is larger on a side closer to the intermediate insulating film than on a side closer to the floating gate electrode.

A transistor which is resistant to a short-channel effect is provided. The transistor includes a first conductor in a ring shape, an oxide semiconductor including a region extending through an inside of a ring of the first conductor, a first insulator between the first conductor and the oxide semiconductor, a second insulator between the first conductor and the first insulator, and a charge trap layer inside the ring of the first conductor. The charge trap layer is inside the second insulator and configured to be in a floating state.

In some implementations, one or more semiconductor processing tools may form a triple-stacked polysilicon structure on a substrate of a semiconductor device. The one or more semiconductor processing tools may form one or more polysilicon-based devices on the substrate of the semiconductor device, wherein the triple-stacked polysilicon structure has a first height that is greater than one or more second heights of the one or more polysilicon-based devices. The one or more semiconductor processing tools may perform a chemical-mechanical polishing (CMP) operation on the semiconductor device, wherein performing the CMP operation comprises using the triple-stacked polysilicon structure as a stop layer for the CMP operation.

A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

A flash memory includes a linear array of flash memory cells having a source region extending along a first direction. Each flash memory cell includes a floating gate disposed adjacent the source region. The linear array of flash memory cells further includes isolation strips disposed between the floating gates of the flash memory cells. An erase gate line extends along the first direction and is disposed over the source region. A control gate line extends along the first direction and is disposed over the isolation strips and over the floating gates of the flash memory cells. The control gate line has a non-straight edge proximate to the source region that is indented away from the source region at least where the control gate line is disposed over the isolation strips.

The present invention discloses a floating-gate type split-gate flash memory device and a manufacturing method thereof. A selection-gate oxide layer and a selection-gate poly layer are sequentially located on the P-type well; a hard mask layer is located on the selection-gate poly layer; a floating-gate dielectric layer is deposited on the hard mask layer; a second floating-gate poly layer is located between an interpoly ONO layer and the floating-gate dielectric layer; a second control-gate poly layer is located on the outer side of the interpoly ONO layer. In the present invention, a coupling mode of CG and FG is changed into coupling combining longitudinal coupling with transverse coupling from original longitudinal coupling; the structure of the device is continuously miniaturized along with the device; longitudinal coupling is gradually reduced; and therefore, the effects of strengthening the CG control ability and reducing electric leakage of the device are achieved.