The disclosure, belonging to the technological field of semiconductor memory, specifically relates to a semi-floating-gate device which comprises at least a semiconductor substrate, a source region, a drain region, a floating gate, a control gate, a perpendicular channel region and a gated p-n junction diode used to connect the floating gate and the substrate. The semi-floating-gate device disclosed in the disclosure using the floating gate to store information and realizing charging or discharging of the floating gate through a gated p-n junction diode boasts small unit area, high chip density, low operating voltage in data storage and strong ability in data retain.

A semiconductor memory device includes string select lines extending in a first direction, vertical pillars connected to the string select lines, sub-interconnections on the string select lines, bitlines connected to the vertical pillars through the sub-interconnections, and upper contact plugs connecting the sub-interconnections to the bitlines. The string select lines include odd and even string select lines alternately arranged in a second direction. The sub-interconnections each connect a pair of vertical pillars respectively connected to one of the odd string select lines and one of the even string select lines that are adjacent to each other. Each of the upper contact plugs is between one of the sub-interconnections and one of the bitlines. Each of the upper contact plugs is arranged more adjacent to one string select line of the adjacent string select lines to which the pair of vertical pillars connected by the sub-interconnections are connected.

Systems and methods for multitasking using touch-sensitive devices are disclosed herein. In one aspect, a method includes: playing video content in a full-screen mode on a touch-sensitive display of an electronic device. While playing the video content in the full-screen mode, the method further includes: receiving a request to display a home screen on the touch-sensitive display. In response receiving the request, the method also includes: (i) displaying the home screen; (ii) resizing the video content to fit within a reduced area of the touch-sensitive display; and (iii) displaying the resized video content overlaying the home screen.

Systems and methods for multitasking using touch-sensitive displays are disclosed. An example method includes: displaying a first application on a touch-sensitive display (TSD) of an electronic device; detecting, via the TSD, a swipe gesture that moves over part of the first application; in response to detecting the swipe gesture, displaying an application selector with a set of affordances, and the application selector is (i) displayed in a predefined portion of the TSD and (ii) overlays at least a portion of the displayed first application; detecting an input at an affordance of the set of affordances; in response to detecting the input: (i) ceasing to display the application selector; (ii) displaying a second application corresponding to the selected affordance in the predefined portion that was previously used to display the application selector; and (iii) resizing the first application to occupy a remaining portion of the TSD adjacent to the predefined portion.

A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.

A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.

A vertical memory device may include a plurality of word lines spaced apart in a first direction, each extending in a second direction perpendicular to the first direction and having a first width in a third direction perpendicular to the first and second directions, a dummy word line over an uppermost word line, including an opening and having a portion thereof with the first width in the third direction, a first string selection line (SSL) and a second string selection line (SSL) over the dummy word line, the first and second SSLs being at substantially the same level along the first direction, each of the first and second SSLs having a second width less than the first width in the third direction, and a plurality of vertical channel structures, each through the word lines, the dummy word line, and one of the first and second SSLs.

A semiconductor device includes a first pillar-shaped semiconductor layer, a first selection gate insulating film, a first selection gate, a first gate insulating film, a first contact electrode, a first bit line connected to an upper portion of the first pillar-shaped semiconductor layer and an upper portion of the first contact electrode, a second pillar-shaped semiconductor layer, a layer including a first charge storage layer, a first control gate, a layer including a second charge storage layer and formed above the first control gate, a second control gate, a second gate insulating film, a second contact electrode having an upper portion connected to an upper portion of the second pillar-shaped semiconductor layer, and a first lower internal line that connects a lower portion of the first pillar-shaped semiconductor layer and a lower portion of the second pillar-shaped semiconductor layer.

Some embodiments include methods of forming vertical memory strings. A trench is formed to extend through a stack of alternating electrically conductive levels and electrically insulative levels. An electrically insulative panel is formed within the trench. Some sections of the panel are removed to form openings. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Charge blocking material and charge-storage material is formed within the cavities. Channel material is formed within the openings and is spaced from the charge-storage material by gate dielectric material. Some embodiments include semiconductor constructions, and some embodiments include methods of forming vertically-stacked structures.

A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.