A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

An object is to provide a semiconductor device with large memory capacity. The semiconductor device includes first to seventh insulators, a first conductor, and a first semiconductor. The first conductor is positioned on a first top surface of the first insulator and a first bottom surface of the second insulator. The third insulator is positioned in a region including a side surface and a second top surface of the first insulator, a side surface of the first conductor, and a second bottom surface and a side surface of the second insulator. The fourth insulator, the fifth insulator, and the first semiconductor are sequentially stacked on the third insulator. The sixth insulator is in contact with the fifth insulator in a region overlapping the first conductor. The seventh insulator is positioned in a region including the first semiconductor and the sixth insulator.

A semiconductor memory device is provided. The semiconductor memory device includes a semiconductor substrate and transistor structures. The transistor structures are disposed on the semiconductor substrate. Each of the transistor structures includes a semiconductor layer, a floating gate, a control gate, a tunneling oxide layer, and an inter-gate dielectric layer. The semiconductor substrate and the semiconductor layer have the same conductivity type and different doping concentrations. The floating gate covers a sidewall of the semiconductor layer and has a curved sidewall opposite the sidewall of the semiconductor layer. The tunneling oxide layer is between the floating gate and the semiconductor substrate and between the first floating gate and the semiconductor layer. A control gate is disposed on the floating gate and an inter-gate dielectric layer is between the control gate and the floating gate and conformally covers the curved sidewall of the first floating gate.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.

A method includes forming a gate structure over a silicon on insulator (SOI) substrate. The SOI substrate comprising: a base semiconductor layer; an insulator layer over the base semiconductor layer; and a top semiconductor layer over the insulator layer. The method further includes depositing a gate spacer layer over a top surface and along a sidewall of the gate structure; etching the gate spacer layer to define a gate spacer on the sidewall of the gate structure; after etching the gate spacer layer, etching a recess into the top semiconductor layer using a first etch process; and after the first etch process, extending the recess further into the top semiconductor layer using a second etch process. The first etch process is different from the second etch process. The method further includes forming a source/drain region in the recess after the second etch process.

Some embodiments include a method of forming an assembly (e.g., a memory array). A first opening is formed through a stack of alternating first and second levels. The first levels contain silicon nitride, and the second levels contain silicon dioxide. Some of the silicon dioxide of the second levels is replaced with memory cell structures. The memory cell structures include charge-storage regions adjacent charge-blocking regions. Tunneling material is formed within the first opening, and channel material is formed adjacent the tunneling material. A second opening is formed through the stack. The second opening extends through remaining portions of the silicon dioxide, and through the silicon nitride. The remaining portions of the silicon dioxide are removed to form cavities. Conductive regions are formed within the cavities. The silicon nitride is removed to form voids between the conductive regions. Some embodiments include memory arrays.

A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

An integrated circuit includes a memory-cell configured to store a piece of data. The memory cell includes a state transistor having a floating gate configured to store a charge representative of the piece of data and a control gate. A capacitive structure includes a first electrically-conductive body coupled to the floating gate, a second electrically-conductive body and a dielectric body between the first and second electrically-conductive bodies. A generation circuit is configured to detect an invasive or non-invasive attack and generate in response thereto a voltage applied to the second electrically-conductive body to generate a leakage current between the first and second electrically-conductive bodies through the dielectric body. The leakage current is applied to the floating gate in order to modify the charge at the floating gate and corrupt the stored piece of data.

An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.