Provided is a semiconductor switching device such that there is a reduction in surge or loss in multiple kinds of semiconductor switching element provided in parallel and of differing turn-on/turn-off operation characteristics. The semiconductor switching device includes a switching circuit unit that includes in parallel multiple kinds of semiconductor switching element having different turn-on/turn-off operation characteristics and turns a main current on and off, a driver circuit that includes a current source terminal and a current sink terminal and outputs drive signals that collectively turn the semiconductor switching elements on and off from the current source terminal and the current sink terminal, and an impedance element that is interposed between the current source terminal and the current sink terminal in the driver circuit and causes timings of operations by which the semiconductor switching elements are turned on and off to differ from each other.

One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.

A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I.sub.1) of the polysilicon resistor providing a first projected range (R.sub.P1)<a thickness of the polysilicon layer and second implanting (I.sub.2) providing a second R.sub.P (R.sub.P2), where R.sub.P2>R.sub.P1. I.sub.2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a CMOS transistor area, and a resistor area. A polysilicon layer is deposited to provide a polysilicon gate area for MOS transistors in the CMOS transistor area, over the BSD class device area, and over the field dielectric for providing a polysilicon resistor in the resistor area. A first mask pattern is formed on the polysilicon layer. Using the first mask pattern, first implanting (I.sub.1) of the polysilicon resistor providing a first projected range (R.sub.P1)<a thickness of the polysilicon layer and second implanting (I.sub.2) providing a second R.sub.P (R.sub.P2), where R.sub.P2>R.sub.P1. I.sub.2 provides a CMOS implant into the semiconductor surface layer in the CMOS transistor area and/or a BSD implant into the semiconductor surface layer in the BSD area.

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.

An apparatus includes a gate drive circuit and a GaN HEMT switch where the gate drive circuit has a gate drive output to produce a gate drive signal in response to a gate control signal. The switch has a gate connected to the gate drive circuit through a gate drive resistor. The gate drive circuit includes a NPN (or NMOS) turn-on transistor and a PNP (or PMOS) turn-off transistor. The gate drive circuit includes a turn-on resistor with a first resistance coupled to the turn-on transistor and a turn-off resistor with a second resistance coupled to the turn-off transistor. The turn-on and turn-off transistors, gate drive resistor, the switching device, but not the turn-on and turn-off resistors are disposed in an integrated circuit to reduce a gate-drive loop inductance. The first and second resistances can be different to adjust the turn-on and turn-off speeds of the switching device.

An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region.

A semiconductor device includes an annular-shaped first frame comprised of a ceramic and forming an inner cavity in which semiconductor elements are disposed. A first electrode is on one side and a second electrode is on another. A second frame in the inner cavity holds the semiconductor elements and is comprised of a resin. A first metallic member is on one side, has an annular shape, and connects the first frame and first electrode. A second metallic member is on the other side, has an annular shape, and connects the first frame and the second electrode. A first elastic body has a first portion between the first metallic member and the second frame and a second portion abutting an inner sidewall of the first frame or overlapping the first frame. A second elastic body has a first portion between the second metallic member and the second frame.

A performance of a semiconductor device including an RC-IGBT is improved. An AlNiSi layer (a layer containing aluminum (Al), nickel (Ni), and silicon (Si)) is formed between a back surface of a semiconductor substrate and a back surface electrode. Thus, a favorable ohmic junction can be obtained between the back surface electrode and an N.sup.+-type layer constituting a cathode region in an embedded diode, and a favorable ohmic junction can be obtained between the back surface electrode and a P-type layer constituting a collector region in an IGBT. The AlNiSi layer contains 10 at % or more of each of the aluminum (Al), the nickel (Ni), and the silicon (Si).

A method of manufacturing a substrate is disclosed. The method comprises: providing a first semiconductor substrate, which includes an at least partially processed CMOS device layer and a layer of first wafer material; bonding a handle substrate to the partially processed CMOS device layer and removing the layer of first wafer material; providing a second semiconductor substrate having a layer of second wafer material which is different to silicon; bonding the first and second semiconductor substrates to form a combined substrate by bonding the layer of second wafer material to the partially processed CMOS device layer; and removing the handle substrate from the combined substrate to expose at least a portion of the partially processed CMOS device layer.