A semiconductor apparatus including a power semiconductor element connected between a first terminal on a high potential side and a second terminal on a low potential side, and controlled to be ON or OFF according to a gate potential thereof; a switch element connected between a control terminal that inputs a control signal for controlling the power semiconductor element and a gate of the power semiconductor element, and controlled to be ON or OFF according to a gate potential thereof; an ON potential supplying section connected between the first terminal and a gate of the switch element, that supplies an ON potential to the gate of the switch element; and an OFF potential supplying section connected between a reference potential and the gate of the switch element, that sets the gate potential of the switch element to an OFF potential in response to a predetermined cutoff condition being satisfied.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region.

A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to control a gate current of the first IGBT, a second switching element that is configured to be able to control a gate current of the second IGBT, and a third switching element that is connected between an electrode of the first IGBT and an electrode of the second IGBT. The control circuit controls a turn on timing and turn off timing.

Provided is an electrostatic protection circuit that has little leakage current under normal operation and allows a trigger voltage to be set comparatively freely, without requiring a special process step. This electrostatic protection circuit is provided with a series circuit including a transistor, a predetermined number of diodes and an impedance element that are connected in series between the first node and the second node, and a discharge circuit configured to send current from the first node to the second node following an increase in a potential difference that occurs between both ends of the impedance element, when the first node reaches a higher potential than the second node and current flows through the series circuit. The predetermined number of diodes are connected between the source and the back gate of the transistor.

This disclosure provides a negative capacitance gate stack structure with a variable positive capacitor to implement a hysteresis free negative capacitance field effect transistors (NCFETs) with improved voltage gain. The gate stack structure provides an effective ferroelectric negative capacitor by using the combination of a ferroelectric negative capacitor and the variable positive capacitor with semiconductor material (such as polysilicon), resulting in the effective ferroelectric negative capacitor's being varied with an applied gate voltage. Our simulation results show that the NCFET with the variable positive capacitor can achieve not only a non-hysteretic I.sub.D-V.sub.G curve but also a better sub-threshold slope.

A semiconductor device includes a switching device region including an active region having a first conductivity-type emitter region formed on an upper surface side of a first conductivity-type substrate, a second conductivity-type base region formed on an upper surface side of the substrate, a second conductivity-type collector layer formed on a lower surface side of the substrate, and a diode region having a second conductivity-type anode layer formed on the upper surface side of the substrate and a first conductivity-type cathode layer formed on the lower surface side of the substrate, wherein the cathode layer is separated from the active region when planarly viewed, and on an upper surface side of the active region, a second conductivity type high-concentration region having an impurity concentration higher than that of the anode layer is formed.

A semiconductor device is provide that includes: a semiconductor body having a first surface, an inner region, and an edge region; a pn junction between a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, the pn-junction extending in a lateral direction of the semiconductor body in the inner region; a recess extending from the first surface in the edge region into the semiconductor body, the recess comprising at least one sidewall; a dielectric filling the recess. In the dielectric, a dielectric number, in the lateral direction, decreases as a distance from the first sidewall increases.

In at least some embodiments, an ultrasound system includes an ultrasound transducer and a bi-directional transistor coupled to the ultrasound transducer. The ultrasound system also includes an ultrasound receiver coupled to the bi-directional transistor. The bi-directional transistor operates to selectively connect the ultrasound transducer to ground and to selectively connect the ultrasound transducer to the ultrasound receiver.

A method of fabricating a laterally diffused metal-oxide-semiconductor (LDMOS) transistor device having a bipolar transistor for electrostatic discharge (ESD) protection includes doping a substrate to form a body region of the LDMOS transistor device in the substrate, the body region having a first conductivity type, forming a doped isolating region of the LDMOS transistor device in the substrate, the doped isolating region having a second conductivity type and surrounding a device area of the LDMOS transistor device in which the body region is disposed, forming a base contact region of the bipolar transistor, the base contact region being disposed within the body region and having the first conductivity type, and doping the substrate to form an isolation contact region for the doped isolating region that defines a collector region of the bipolar transistor, to form source and drain regions of the LDMOS transistor device in the substrate, and to form an emitter region of the bipolar transistor within the body region.

A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.