A p-type well is formed in a semiconductor substrate, and an n.sup.+-type semiconductor region and a p.sup.+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n.sup.+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p.sup.+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n.sup.+-type semiconductor region and the p.sup.+-type semiconductor region, and at least a part of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n.sup.+-type semiconductor region.

The betas of the bipolar transistors in a BiCMOS semiconductor structure are increased by forming the emitters of the bipolar transistors with two implants: a source-drain implant that forms a first emitter region at the same time that the source and drain regions are formed, and an additional implant that forms a second emitter region at the same time that another region is formed. The additional implant has an implant energy that is greater than the implant energy of the source-drain implant.

An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a fifth insulating film and a sixth insulating film around the second dummy gate; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film around the pillar-shaped semiconductor layer, depositing metal, and performing etch back to form a gate electrode and a gate line; and a sixth step of forming a first diffusion layer in an upper portion of the pillar-shaped semiconductor layer.

Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

The present application teaches, among other innovations, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). A base drive circuit is described which provides high-impedance drive to the base contact region on whichever side of the device is operating as the collector (at a given moment). (The B-TRAN, unlike other bipolar junction transistors, is controlled by applied voltage rather than applied current.) The preferred implementation of the drive circuit is operated by control signals to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with a low voltage drop (the transistor-ON state). In some but not necessarily all preferred embodiments, an adjustable low voltage for the gate drive circuit is provided by a self-synchronizing rectifier circuit. Also, in some but not necessarily all preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while the base current at that terminal is monitored, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.

A bipolar junction transistor includes a first well region having a first conductive type, a second well region disposed adjacent to the first well region and having a second conductive type, a base disposed on the first well region and having the first conductive type, an emitter disposed on the first well region and having the second conductive type, and a collector disposed on the second well region and having the second conductive type. The first well region comprises a first impurity region and a second impurity region having an impurity concentration lower than that of the first impurity region. The base is disposed on the first impurity region, and the emitter is disposed on the second impurity region.

A method for manufacturing a bipolar transistor, including the steps of: forming a first surface-doped region of a semiconductor substrate having a semiconductor layer extending thereon with an interposed first insulating layer; forming, at the surface of the device, a stack of a silicon layer and of a second insulating layer; defining a trench crossing the stack and the semiconductor layer opposite to the first doped region, and then an opening in the exposed region of the first insulating layer; forming a single-crystal silicon region in the opening; forming a silicon-germanium region at the surface of single-crystal silicon region, in contact with the remaining regions of the semiconductor layer and of the silicon layer; and forming a second doped region at least in the remaining space of the trench.

Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.