A metal-insulator-metal (MIM) capacitor includes, in cross-sectional view, a first metal plate, a second metal plate, a third metal plate, and high-k material contacting the first metal plate, the second metal plate, and the third metal plate, in a manner achieved by using a single etching/mask pattern for an etching and deposition process to form the second metal plate, the third metal plate, the high-k material layer, and contact with the first metal plate.

A semiconductor device is formed by forming a deep trench in a substrate and a dielectric liner on sidewalls of the deep trench. A first undoped polysilicon layer is formed on the semiconductor device, extending into the deep trench on the dielectric liner, but not filling the deep trench. Dopants are implanted into the first polysilicon layer. A second layer of polysilicon is formed on the first layer of polysilicon. A thermal drive anneal activates and diffuses the dopants. In one version, the dielectric liner is removed at the bottom of the deep trench before the first polysilicon layer is formed, so that the polysilicon in the deep trench provides a contact to the substrate. In another version, the polysilicon in the deep trench is isolated from the substrate by the dielectric liner.

A semiconductor memory structure includes a substrate including a memory cell region, a peripheral circuit region and a cell edge region defined thereon, and the cell edge region is defined in between the memory cell region and the peripheral circuit region. The semiconductor memory structure includes a plurality of active regions formed in the memory cell region, the cell edge region and the peripheral circuit region, and at least a dummy bit line formed on the active regions in the cell edge region. The dummy bit line is extended along a first direction and overlaps at least two active regions in a second direction. And the first direction and the second direction are perpendicular to each other. The dummy bit line includes a first inner line portion and an outer line portion, and the first inner line portion and the outer line portion include different widths and different spacers.

A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

A metal-insulator-metal capacitor includes a bottom electrode comprising a nitride of a metal, an insulator disposed on the bottom electrode and comprising an oxide of the metal, and a top electrode disposed on the insulator and comprising a nitride of the metal. Optionally, the insulator further includes an oxynitride of the metal, at least a portion of the oxynitride being characterized by a progressive change in the ratio of oxygen to nitrogen over thickness.

In fabrication of an integrated circuit having a layer with a plurality of conductive interconnects, a layer of a substrate is polished to provide the layer of the integrated circuit. The layer of the substrate includes conductive lines to provide the conductive interconnects. The layer of the substrate includes a closed conductive loop formed of a conductive material in a trench. A depth of the conductive material in the trench is monitored using an inductive monitoring system and a signal is generated. Monitoring includes generating a magnetic field that intermittently passes through the closed conductive loop. A sequence of values over time is extracted from the signal, the sequence of values representing the depth of the conductive material over time.

The present disclosure provides a capacitor structure, including a substrate having a conductive region; a trench in the conductive region and having a bottom portion and an inner sidewall portion; a spacer over the inner sidewall portion of the trench; a first conductive layer over the bottom portion and the spacer in the trench; a first dielectric layer over the first conductive layer and in the trench; a second conductive layer over the first dielectric layer and in the trench; and a second dielectric layer over the second conductive layer and in the trench, wherein the spacer comprises an angle in a range of from about 85 to about 89 degrees with respect to the bottom portion of the trench and comprises a flared opening opposite to the bottom portion of the trench. The present disclosure also provides a method for manufacturing the capacitor structure.

A semiconductor device includes a substrate having a field region disposed therein that defines an active region of the substrate, the active region comprising a pillar-shaped bit line contact region having an upper surface disposed at a higher level than an upper surface of the field region. An interlayer insulating layer is disposed on the substrate and covers the field region. A bit line is disposed in a trench in the interlayer insulating layer above the pillar-shaped bit line contact region and electrically connected thereto.

Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material.