A method is provided for forming a metal-insulator-metal capacitor in a replacement metal gate module. The method includes providing a gate cap formed on a gate. The method further includes removing a portion of the gate cap and forming a recess in the gate. A remaining portion of the gate forms a first electrode of the capacitor. The method also includes depositing a dielectric on remaining portions of the gate cap and the remaining portion of the gate. The method additionally includes depositing a conductive material on the dielectric. The method further includes removing a portion of the conductive material and portions of the dielectric to expose a remaining portion of the conductive material and a remaining portion of the dielectric. The remaining portion of the conductive material forms a second electrode of the capacitor. The remaining portion of the dielectric forms an insulator of the capacitor.

Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Techniques for a semiconductor device are provided. Techniques are directed to forming a semiconductor device by: forming a fin structure in a substrate, forming a protective layer over an upper portion of the fin structure, the protective layer having an etch selectivity with respect to a material of the fin structure, and performing an undercut etch so as to remove a lower portion of the fin structure below the protective layer, thereby defining a nanowire structure from the fin structure.

Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.

According to one embodiment, a method of manufacturing a semiconductor device comprises forming a semiconductor layer on a substrate, forming a first insulating film on the semiconductor layer, forming a metal layer on the first insulating film, forming a first portion and a second portion in the metal layer, implanting an impurity into the semiconductor layer by using the first portion and the second portion as masks, forming a gate electrode by reducing the second portion in addition to removing the first portion, and implanting an impurity into the semiconductor layer by using the gate electrode as a mask.

A test probe structure having a planar surface and contact locations matched to test hardware is provided. The fabrication of the test probe structure addresses problems related to the possible deformation of base substrates during manufacture. Positional accuracy of contact locations and planarity of base substrates is achieved using dielectric layers, laser ablation, injection molded solder or redistribution layer wiring, and planarization techniques.

A method of manufacturing a capacitive device. The method includes doping a substrate to form a well region, forming M shoulder portions and (M1) trenches in the substrate, depositing (M1) sets of stacked layers along an upper surface of each shoulder portion of the M shoulder portions, sidewalls of the (M1) trenches, and a bottom surface of each trench of the (M1) trenches, and etching a plurality of contact holes variously exposing the well region or conductive layers of the (M1) sets of stacked layers by N patterned masks. An m-th trench of the (M1) trenches is between an m-th shoulder portion and an (m+1)-th shoulder portion of the M shoulder portions. M is a positive integer equal to or greater than 2 and m is a positive integer from 1 to (M1). N is a positive integer less than M. Each contact hole of the plurality of contact holes is directly on or above a corresponding shoulder portion of the M shoulder portions.

Provided is a method of forming a decoupling capacitor device and the device thereof. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

A method for the formation of a MIM capacitor on a substrate is described. Initially, a target comprising a metal is sputtered in the presence of nitrogen to form at least a portion of a bottom electrode. Next, the target is further sputtered in the presence of oxygen to form at least a part of an insulator. Finally, the target is even further sputtered in the presence of nitrogen to form a portion of a top electrode. The insulator is sandwiched between the bottom electrode and the top electrode. The formation of the bottom electrode, the insulator, and the top electrode is performed in a sputter deposition chamber without removing the substrate therefrom.