A photoconductive device that generates or detects terahertz radiation includes a semiconductor layer; a structure portion; and an electrode. The semiconductor layer has a thickness no less than a first propagation distance and no greater than a second propagation distance, the first propagation distance being a distance that the surface plasmon wave propagates through the semiconductor layer in a perpendicular direction of an interface between the semiconductor layer and the structure portion until an electric field intensity of the surface plasmon wave becomes 1/e times the electric field intensity of the surface plasmon wave at the interface, the second propagation distance being a distance that a terahertz wave having an optical phonon absorption frequency of the semiconductor layer propagates through the semiconductor layer in the perpendicular direction until an electric field intensity of the terahertz wave becomes 1/e.sup.2 times the electric field intensity of the terahertz wave at the interface.

A composition for forming a passivation layer, comprising a compound represented by Formula (I): M(OR.sup.1).sub.m. In Formula (I), M comprises at least one metal element selected from the group consisting of Nb, Ta, V, Y and Hf, each R.sup.1 independently represents an alkyl group having from 1 to 8 carbon atoms or an aryl group having from 6 to 14 carbon atoms, and m represents an integer from 1 to 5.

An electronic component includes a base, a laminate of a plurality of conductive metal material layers, and a solder layer made of AuSn alloy solder. The laminate is disposed on the base. The solder layer is disposed on the laminate. The laminate includes a surface layer made of Au as the conductive metal material layer constituting an outermost layer. The surface layer includes a solder layer-disposing region in which the solder layer is disposed and a solder layer-empty region in which the solder layer is not disposed. The solder layer-disposing region and the solder layer-empty region are spatially separated from each other.

Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

Structures and techniques introduced here enable the design and fabrication of photodetectors (PDs) and/or other electronic circuits using typical semiconductor device manufacturing technologies meanwhile reducing the adverse impacts on PDs' performance. Examples of the various structures and techniques introduced here include, but not limited to, a pre-PD homogeneous wafer bonding technique, a pre-PD heterogeneous wafer bonding technique, a post-PD wafer bonding technique, their combinations, and a number of mirror equipped PD structures. With the introduced structures and techniques, it is possible to implement PDs using typical direct growth material epitaxy technology while reducing the adverse impact of the defect layer at the material interface caused by lattice mismatch.

Approaches for silicon photonics integration are provided. A method includes: forming at least one encapsulating layer over and around a photodetector; thermally crystallizing the photodetector material after the forming the at least one encapsulating layer; and after the thermally crystallizing the photodetector material, forming a conformal sealing layer on the at least one encapsulating layer and over at least one device. The conformal sealing layer is configured to seal a crack in the at least one encapsulating layer. The photodetector and the at least one device are on a same substrate. The at least one device includes a complementary metal oxide semiconductor device or a passive photonics device.

A system and method for a multi-sensor pixel architecture for use in a digital imaging system is described. The system includes at least one semiconducting layer for absorbing radiation incident on opposites of the at least one semiconducting layer along with a set of electrodes on one side of the semiconducting layer for transmitting a signal associated with the radiation absorbed by the semiconducting layer.

According to a photodetector includes a first light detection layer and a reflective layer. The first light detection layer has a first surface and a second surface on a side opposite to the first surface. The first light detection layer includes a first light detection area including a p-n junction of a p-type semiconductor layer containing Si and an n-type semiconductor layer containing Si. The reflective layer arranged on a second surface side of the first light detection layer so as to be opposed to the first light detection area. The reflective layer reflects at least part of light in a near-infrared range.

A semiconductor device is disclosed, which includes: at least one device layer being a crystallized layer for example including: a superlattice layer and/or a layer of group III-V semiconductor materials; and a passivation structure comprising one or more layers wherein at least one layer of the passivation structure is a passivation layer grown in-situ in a crystallized form on top of the device layer, and at least one of the one or more layers of the passivation structure includes material having a high density of surface states which forces surface pinning of an equilibrium Fermi level within a certain band gap of the device layer, away from its conduction and valence bands.

A method for producing an optoelectronic semiconductor component having a plurality of image points and an optoelectronic component are disclosed. In an embodiment the method includes providing a semiconductor layer sequence including an n-conducting semiconductor layer, an active zone, and a p-conducting semiconductor layer; applying a first layer sequence, wherein the first layer sequence is divided into a plurality of regions which are arranged laterally spaced with respect to each other on a top surface of the p-conducting semiconductor layer; c) applying a second insulating layer; partially removing the p-conducting semiconductor layer and the active zone, in such a way that the n-conducting semiconductor layer is exposed at points and the p-conducting semiconductor layer is divided into individual regions which are laterally spaced with respect to each other, wherein each of the regions comprises a part of the p-conducting semiconductor layer and a part of the active zone.