A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A device includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, an isolation layer over the low-k dielectric layer, and a work function layer over the isolation layer. The work function layer is an n-type work function layer. The device further includes a low-dimensional semiconductor layer on a top surface and a sidewall of the work function layer, source/drain contacts contacting opposing end portions of the low-dimensional semiconductor layer, and a dielectric doping layer over and contacting a channel portion of the low-dimensional semiconductor layer. The dielectric doping layer includes a metal selected from aluminum and hafnium, and the channel portion of the low-dimensional semiconductor layer further comprises the metal.

A semiconductor device may include a transistor structure. The transistor structure may include a metal structure extending along a vertical direction; a gate dielectric layer around the metal structure; a channel layer around the gate dielectric layer; a first metal electrode disposed below the metal structure and in electrical contact with a first end of the channel layer; a second metal electrode disposed above the metal structure and in electrical contact with a second end of the channel layer; and a third metal electrode disposed above and in electrical contact with the metal structure.

A device includes a substrate, a dielectric layer, carbon nanotubes (CNTs), a gate structure, gate spacers, source/drain epitaxy structures, and source/drain contacts. The dielectric layer is over the substrate. The CNTs are over the dielectric layer. The gate structure is over the substrate, in which the gate structure covers the CNTs from a top view. The gate spacers are on opposite sidewalls of the gate structure. The source/drain epitaxy structures are over the substrate and on opposite sides of the gate structure, in which in a cross-sectional view, the source/drain epitaxy structures are in contact with opposite ends of the CNTs and opposite sidewalls of the dielectric layer. The source/drain contacts are over the source/drain epitaxy structures, respectively.

Various embodiments of the present application are directed towards an integrated chip (IC) including a lower dielectric structure over a semiconductor substrate. A gate structure is over the lower dielectric structure. The gate structure comprises a first surface opposite a second surface. A first semiconductor layer is arranged between the first surface of the gate structure and the lower dielectric structure. A second semiconductor layer is over the second surface of the gate structure.

A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a plurality of device units. The device units includes a first device unit, and the first device unit includes a substrate including two source/drain regions and a gate region disposed between the two source/drain regions; a gate electrode layer disposed on the gate region, and a top surface of the gate electrode layer is coplanar to top surfaces of the two source/drain regions; a first channel layer disposed on the gate electrode layer, wherein the first channel layer includes a 2D semiconductor material; two air spacers disposed below the first channel layer and between the gate region and the two source/drain regions, respectively.

A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.

A semiconductor device includes a semiconductor pattern protruding in a direction perpendicular to a top surface of a substrate and having an inner surface and an outer surface that stand opposite to each other in a first direction parallel to the top surface of the substrate, a gate dielectric layer covering the inner surface and the outer surface of the semiconductor pattern and extending onto a top surface of the semiconductor pattern, a gate electrode on the gate dielectric layer and covering the outer surface, the top surface, and the inner surface of the semiconductor pattern, and an auxiliary pattern between the gate dielectric layer and the inner surface of the semiconductor pattern. The outer surface of the semiconductor pattern is in contact with the gate dielectric layer. The inner surface of the semiconductor pattern is in contact with the auxiliary pattern.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.

A thin-film electronic component includes a first terminal, a second terminal, and a first current path between the first terminal and the second terminal, wherein the first current path is formed from a first segment of a first material and a first segment of a second material arranged in series between the first terminal and the second terminal.