Disclosed herein is a new and improved system and method for fabricating diamond films by first seeding a surface of a transparent substrate. A diamond layer that is at least one of nanocrystalline and ultrananocrystalline can be deposited upon the surface of the transparent substrate and both the diamond layer and the transparent substrate modified to incorporate substitutional atoms.

A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices.

Devices and methods are disclosed, related to high power diode switches. In some embodiments, a radio-frequency switch circuit can include a first switchable path implemented between a pole and a first throw, the first switchable path including one or more PIN diodes, and a second switchable path implemented between the pole and a second throw, the second switchable path including one or more PIN diodes. The radio-frequency switch circuit can further include a switchable shunt path implemented between the second throw and a ground, the switchable shunt path including at least one shunt PIN diode and a capacitance between the second throw and the at least one shunt PIN diode. The pole can be an antenna port, and the first and second throws can be transmit and receive ports, respectively.

A semiconductor device includes an insulated-gate bipolar transistor (IGBT) structure and a metal-oxide-semiconductor (MOS) transistor structure integrated in a wafer. The MOS transistor structure is connected in parallel with the IGBT structure. A thickness of a trench insulating layer in the MOS transistor structure is less than a thickness of a trench insulating layer in the IGBT structure.

A semiconductor device of embodiments includes: a semiconductor layer including a first trench, a second trench, a first semiconductor region of a first conductive type, a second semiconductor region of a second conductive type provided between a first face and the first semiconductor region, between the first trench and the second trench, and in contact with the second trench, a third semiconductor region of a first conductive type provided between the first trench and the second semiconductor region, a fourth semiconductor region of a second conductive type provided between the third semiconductor region and the first face, and a fifth semiconductor region of a second conductive type provided between the second semiconductor region and the first face, spaced from the fourth semiconductor region, in contact with the second trench; a first electrode on a first face side; and a second electrode on a second face side.

A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.010.sup.11 cm.sup.3.

A semiconductor device according to the present disclosure includes: a semiconductor substrate with a first main surface and a second main surface; a drift layer of a first conductivity type formed in the semiconductor substrate; a first impurity diffusion layer of a second conductivity type formed on the drift layer to be closer to the first main surface; and a buffer layer of the first conductivity type formed on the drift layer to be closer to the second main surface and higher in peak impurity concentration than the drift layer. The drift layer has a first trap, a second trap, and a third trap, whose energy level each is lower than energy at a bottom of a conduction band by 0.246 eV, 0.349 eV, and 0.470 eV. The second trap has trap density of equal to or greater than 2.010.sup.11 cm.sup.3.

A semiconductor device including a drift region and a buffer region is provided. The drift region of a first conductivity type is provided in a semiconductor substrate. The buffer region of the first conductivity type includes at least six peaks in a doping concentration distribution in a depth direction of the semiconductor substrate. A curve connecting the at least six peaks includes an upwardly-convex portion.

A semiconductor device including a drift region and a buffer region is provided. The drift region of a first conductivity type is provided in a semiconductor substrate. The buffer region of the first conductivity type includes at least six peaks in a doping concentration distribution in a depth direction of the semiconductor substrate. A curve connecting the at least six peaks includes an upwardly-convex portion.

A semiconductor integrated circuit (IC) device includes both a transistor and a vertical diode. In some examples, the transistor includes a backside source/drain (S/D) contact and the vertical diode includes a backside bottom contact. The backside S/D contact and the backside bottom contact may be electrically connected to a backside BEOL network. The transistor may further include a S/D region that includes an upper S/D portion and a trench S/D portion that has a higher dopant concentration relative to the upper portion. The backside S/D contact may be connected to the trench S/D portion of the S/D region. The vertical diode may include a bottom doped region which may be simultaneously formed along with the trench S/D portion and may be composed of substantially the same materials. The backside bottom contact may be directly connected to the bottom doped region of the vertical diode.