An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

According to various embodiments, a method may include: structuring a semiconductor region to form a structured surface of the semiconductor region; disposing a dopant in the semiconductor region; and activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially.

An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired.

A semiconductor device includes a first semiconductor region having first charge carriers of a first conductivity type and a second semiconductor region having second charge carriers. The first semiconductor region includes a transition region in contact with the second semiconductor region, the transition region having a first concentration of the first charge carriers, a contact region having a second concentration of the first charge carriers, wherein the second concentration is higher than the first concentration, and a damage region between the contact region and the transition region. The damage region is configured for reducing lifetime and/or mobility of the first charge carriers of the damage region as compared to the lifetime and/or the mobility of the first charge carriers of the contact region and the transition region.

A semiconductor device includes a diode region and an IGBT region. The diode region includes a front side anode region, an n-type diode barrier region, an n-type diode pillar region reaching the diode barrier region through the front side anode region, and a p-type back side anode region separated from the front side anode region by the diode barrier region. The IGBT region includes a front side body region, an n-type IGBT barrier region, and a back side body region separated from the front side body region by the IGBT barrier region. When a gate-off voltage is applied to a gate electrode, a resistance between the IGBT barrier region and the emitter electrode is higher than a resistance between the diode barrier region and the anode electrode.

This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

A semiconductor device includes an IGBT region with a bottom-body region on a front surface side of an IGBT drift region, an IGBT barrier region on a front surface side of the bottom-body region, and a top-body region on a front surface side of the IGBT barrier region. A diode region is include with a bottom-anode region on a front surface side of the diode drift region, a diode barrier region on a front surface side of the bottom-anode region, a top-anode region on a front surface side of the diode barrier region, and a pillar region extending from the front surface of the semiconductor substrate, piercing the top-anode region, and reaching the diode barrier region, and connected to the front surface electrode and the diode barrier region. An impurity concentration of the top-body region is lower than an impurity concentration of the bottom-anode region.

An electronic device includes a solid body of SiC having a surface and having a first conductivity type. A first implanted region and a second implanted region have a second conductivity type and extend into the solid body in a direction starting from the surface and delimit between them a surface portion of the solid body. A Schottky contact is on the surface and in direct contact with the surface portion. Ohmic contacts are on the surface and in direct contact with the first and second implanted regions. The solid body includes an epitaxial layer including the surface portion and a bulk portion. The surface portion houses a plurality of doped sub-regions which extend in succession one after another in the direction, are of the first conductivity type, and have a respective conductivity level higher than that of the bulk portion.

An integrated circuit device includes: a substrate including a first surface and a second surface that is opposite to the first surface; and a diode structure including: an upper semiconductor layer disposed on the first surface of the substrate and including a first dopant of a first conductivity type; a lower semiconductor layer disposed on the second surface of the substrate and including a second dopant of a second conductivity type that is different from the first conductivity type; and a first well region provided in a portion of the substrate that is between the upper semiconductor layer and the lower semiconductor layer, wherein the first well region is in contact with the upper semiconductor layer or the lower semiconductor layer.

A method of manufacturing a vertical power semiconductor device includes forming a drift region in a semiconductor body having a first main surface and a second main surface opposite to the first main surface along a vertical direction, the drift region including platinum atoms, and forming a field stop region in the semiconductor body between the drift region and the second main surface, the field stop region including a plurality of impurity peaks, wherein a first impurity peak of the plurality of impurity peaks is set a larger concentration than a second impurity peak of the plurality of impurity peaks, wherein the first impurity peak includes hydrogen and the second impurity peak includes helium.