Provided is a manufacturing method for a semiconductor device including a transistor portion and a diode portion. The manufacturing method includes forming, on an upper surface of a semiconductor substrate including a bulk donor, an emitter region of the transistor portion and an anode region of the diode portion as an active region, performing ion implantation of a first dopant of a first conductivity type to the transistor portion and the diode portion from a lower surface of the semiconductor substrate, and performing ion implantation of a second dopant of the first conductivity type to the transistor portion from the lower surface of the semiconductor substrate.

Silicon carbide junction barrier Schottky diode disclosed. Silicon carbide junction barrier Schottky diode includes a first conductivity-type substrate, a first conductivity-type epitaxial layer, being formed by epitaxial growth of silicon carbide doped with a first conductivity-type impurity on the first conductivity-type substrate, a charge injection region, being formed on the first conductivity-type epitaxial layer and doped at a concentration of the first conductivity-type impurity higher than that of the first conductivity-type epitaxial layer, a second conductivity-type junction region, being formed on the first conductivity-type epitaxial layer so as to contact the charge injection region, a Schottky metal layer, being formed on the charge injection region and the second conductivity-type junction region, an anode electrode, being formed on the Schottky metal layer, and a cathode electrode, being formed under the first conductivity-type substrate.

A semiconductor device includes a semiconductor substrate, a drift layer of a first conductivity type, a buffer layer of the first conductivity type, a first semiconductor layer, and a second semiconductor layer. The first semiconductor layer and the second semiconductor layer are provided on the side of the second main surface of the semiconductor substrate with respect to the buffer layer. The first semiconductor layer and the second semiconductor layer are arranged in this order in a direction from the second main surface toward the first main surface of the semiconductor substrate. The first semiconductor layer and the second semiconductor layer have conductivity types identical to each other. The second semiconductor layer has a larger number of atoms of impurities per unit volume than the first semiconductor layer.

Provided is a semiconductor device including: a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate runner portion configured to be electrically connected to an end portion of the first trench portion; and a second gate runner portion configured to be electrically connected to the first gate runner portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate runner portion is larger than a resistivity per unit length of the second gate runner portion.

A reverse conducting power semiconductor device includes a plurality of thyristor cells and a freewheeling diode are integrated in a semiconductor wafer. The freewheeling diode includes a diode anode layer, a diode anode electrode, a diode cathode layer, and a diode cathode electrode. The diode cathode layer includes diode cathode layer segments, each of which is stripe-shaped and arranged within a corresponding stripe-shaped first diode anode layer segment such that a longitudinal main axis of each diode cathode layer segment extends along the longitudinal main axis of the corresponding one of the first diode anode layer segments.

Semiconductor structures and manufacturing methods thereof. A semiconductor structure includes: a first epitaxial layer; a bonding layer, on first epitaxial layer and provided with a first through-hole exposing first epitaxial layer; a silicon substrate, on a side of bonding layer away from first epitaxial layer, first epitaxial layer and the silicon substrate being bonded through the bonding layer; a through-silicon-via, in silicon substrate, through-silicon-via communicating with first through-hole; a second epitaxial layer, on first epitaxial layer exposed by first through-hole; a first electrode, on a side of first epitaxial layer away from bonding layer, and electrically coupled with first epitaxial layer; a second electrode, on a side of second epitaxial layer away from first epitaxial layer, and electrically coupled with second epitaxial layer.

In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 m or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

A semiconductor device includes a diode section. At least some of a plurality of diode mesas in the diode section are coupled to the drift region via a second anode region electrically connected to the emitter terminal of the semiconductor device. The second anode region extends deeper along the vertical direction as compared to trenches in the diode section.

In a power semiconductor device, the present disclosure is intended to control tradeoff characteristics while realizing operation in a high-speed side range of the tradeoff characteristics without depending on a carrier lifetime control technique. An n+ cathode layer includes a first n+ cathode layer contacting a second metal layer, and a second n+ cathode layer provided between the first n+ cathode layer and an n buffer layer while contacting the first n+ cathode layer and the n buffer layer. Crystal defect density in the first n+ cathode layer is higher than crystal defect density in the second n+ cathode layer. The n+ cathode layer is absent in an intermediate region and a terminal region.