A semiconductor device includes a semiconductor layer disposed at a substrate and a plurality of active cells disposed at the semiconductor layer. Each active cell includes a trench extending into the semiconductor layer and a body region disposed in the semiconductor layer adjacent to a sidewall of the trench and at a first depth below the surface of the semiconductor layer. The semiconductor device further includes a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells. The termination cell includes a trench extending into the semiconductor layer, and further includes a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second depth less than the first depth. The body regions of the active cells and of the termination cell have a conductivity type different than that of the semiconductor layer.

A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

A semiconductor device includes a trench formed in an epitaxial layer and an oxide layer that lines the sidewalls of the trench. The thickness of the oxide layer is non-uniform, so that the thickness of the oxide layer toward the top of the trench is thinner than it is toward the bottom of the trench. The epitaxial layer can have a non-uniform dopant concentration, where the dopant concentration varies according to the thickness of the oxide layer.

A trench power MOSFET and a manufacturing method thereof are provided. The gate of the trench power MOSFET includes an upper doped region, a lower doped region and a middle region interposed therebetween. The upper has a conductive type reverse to that of the lower doped region, and the middle region is an intrinsic or lightly-doped region to form a PIN, P.sup.+/N.sup. or N.sup.+/P.sup. junction. As such, when the trench power MOSFET is in operation, a junction capacitance formed at the PIN, P.sup.+/N.sup. or N.sup.+/P.sup. junction is in series with the parasitic capacitance. Accordingly, the gate-to-drain effective capacitance may be reduced.

A wide bandgap semiconductor power transistor comprising an epitaxial layer of a first conductivity type, at least one well region of a second conductivity type formed in a selected area of the epitaxial layer, at least one terminal region, in particular a source region, of the first conductivity type formed in or adjacent to the at least one well region, at least one terminal electrode, in particular a source electrode, formed at least partly on a surface of a first part of the at least one terminal region, and at least one resistive region formed within the at least one terminal region, the at least one resistive region comprising amphoteric impurities.

A method for manufacturing a semiconductor device is provided. A gate oxide layer is formed over a high-voltage N-type well region, an N-type well region and a P-type well region. The gate oxide layer includes a first layer portion and a second layer portion. The first and second layer portions have different thicknesses. A main gate is formed on the first layer portion and the second layer portion. At least one split gate is formed on the second layer portion, and the main gate and the split gate extend along an interface between the high-voltage N-type well region and the P-type well region. An inter-level dielectric (ILD) layer is formed over the main gate and the split gate. A plurality of connecting features penetrating the ILD layer to contact the main gate and the split gate are formed. An electrode is formed to contact the connecting features.

An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. An impurity concentration of the n-type semiconductor region is lower than an impurity concentration of the n-type source region. A gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.

A semiconductor device includes a substrate comprising a first surface and a second surface positioned on an opposite side of the substrate. A first gate structure is located above the first surface of the substrate and a second gate structure is located above the first surface of the substrate, adjacent to the first gate structure. A first dielectric layer covers the first gate structure, the second gate structure, and the first surface of the substrate. The first dielectric layer has a first opening between the first gate structure and the second gate structure. A current spreading layer is located at a bottom of the first opening. The current spreading layer has a first width approximately equal to a width of the bottom of the first opening. A conductive plug is located between the first gate structure and the second gate structure and in contact with the current spreading layer.

A process for manufacturing a vertical conduction MOSFET device including a body of silicon carbide having a first conductivity type and a face. A metallization region extends on the face of the body. A body region of a second conductivity type extends in the body, from the face of the body, along a first direction parallel to the face and along a second direction transverse to the face. A source region of the first conductivity type extends towards the inside of the body region, from the face of the body, and has a first portion and a second portion. The first portion has a first doping level and extends in direct electrical contact with the metallization region. The second portion has a second doping level and extends in direct electrical contact with the first portion of the source region. The second doping level is lower than the first doping level.

Provided is a nitride semiconductor device including a p-type region having a high effective acceptor concentration while exhibiting good electrical characteristics, and a method of manufacturing the same. The nitride semiconductor device includes: a nitride semiconductor; and a p-type region provided in the nitride semiconductor. The p-type region includes an acceptor element and entirely has a concentration in a range of 510.sup.18 cm.sup.3 or higher and 110.sup.21 cm.sup.3 or lower. The p-type region includes a segregation part in which the acceptor element is partly segregated, and a matrix in which the acceptor element is not segregated. The concentration of the acceptor element in the segregation part is 4.6 times or smaller as high as that in the matrix.