Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates.

The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in the memory region, a logic gate stack disposed in the logic region, and a non-volatile memory disposed in the recess. The non-volatile memory includes at least two floating gates and at least two control gates disposed on the floating gates, where each floating gate has a step-shaped bottom, and the step-shaped bottom includes a first bottom surface and a second bottom surface lower than the first bottom surface.

A method for forming a semiconductor device structure is provided. The method includes forming a mask layer over a substrate. The method includes forming a first isolation structure and a second isolation structure passing through the mask layer and penetrating into the substrate. The method includes thinning the mask layer to expose a first portion of the first isolation structure and a second portion of the second isolation structure. The method includes partially removing the first portion, the second portion, the third portion, and the fourth portion. The method includes removing the thinned mask layer. The method includes forming a first gate over the substrate and between the first isolation structure and the second isolation structure. The method includes forming a dielectric layer over the first gate. The method includes forming a second gate over the dielectric layer and above the first gate.

An insulating film made of the same material as that of a gate insulating film is formed so as to cover one sidewall of a control gate on a conducting film for floating gate. By selectively removing the conducting film for floating gate with the insulating film as a mask, a floating gate is formed from the conducting film for floating gate, and a portion of the gate insulating film is exposed at the floating gate. A nitrogen introduced portion is formed by introducing nitrogen into the exposed portion of the gate insulating film. Then, the insulating film is removed to expose an upper surface of a lateral protrusion of the floating gate. An erase gate is formed so as to face the upper surface and a side surface of the lateral protrusion.

A method of manufacturing a semiconductor device is provided which includes providing a semiconductor layer having a first area and a second area separated from the first area by an isolation structure, forming a protection layer on the isolation structure, forming at least partly a memory device in and on the first area, removing the protection layer, and forming a field effect transistor (FET) in and over the second area after the removal of the protection layer.

A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

Semiconductor structures are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.

According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.

A semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode.

A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a floating gate is removed by using a spacer insulating film, a first insulating film, and a second insulating film as a mask. A floating gate having a tip portion is formed from the conductive layer for the floating gate, and a part of an insulating layer for a gate insulating film is exposed from the floating gate. The tip portion of the floating gate is further exposed by selectively removing the second insulating film among the second insulating film, the insulating layer for the gate insulating film, and the spacer insulating film.