Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

Methods, systems and apparatus for memory devices with discharging circuits are provided. In one aspect, a semiconductor device includes a semiconductor substrate, one or more discharging circuits arranged on the semiconductor substrate, one or more common source line (CSL) layers conductively coupled to the one or more discharging circuits, and a memory array having a three-dimensional (3D) array of memory cells arranged in a plurality of vertical channels on the one or more CSL layers. Each of the plurality of vertical channels includes a respective string of memory cells, and each of the one or more CSL layers is conductively coupled to corresponding strings of memory cells. Each of the one or more discharging circuits includes one or more transistors that are disabled by one or more corresponding conductive lines through the memory array.

Disclosed are a semiconductor device and an electronic system including the same. The semiconductor device may include a peripheral circuit structure including peripheral circuits that are on a semiconductor substrate, and first bonding pads that are electrically connected to the peripheral circuits, and a cell array structure including a memory cell array including memory cells that are three-dimensionally arranged on a semiconductor layer, and second bonding pads that are electrically connected to the memory cell array and are coupled to the first bonding pads. The cell array structure may include a resistor pattern positioned at the same level as the semiconductor layer, a stack including insulating layers and electrodes that are vertically and alternately stacked on the semiconductor layer, and vertical structures penetrating the stack.

Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device includes a stack structure including electrodes vertically stacked on a semiconductor layer, a source semiconductor pattern between the semiconductor layer and the stack structure, a support semiconductor pattern between the stack structure and the source semiconductor pattern, and a vertical structure penetrating the stack structure, the support semiconductor pattern, and the source semiconductor pattern. The vertical structure includes a vertical channel pattern in which a part of a sidewall is in contact with the source semiconductor pattern. The vertical channel pattern includes an upper portion adjacent to the stack structure, a lower portion adjacent to the source semiconductor pattern, and a middle portion adjacent to the support semiconductor pattern. The upper portion has a first diameter. The lower portion has a second diameter. The middle portion has a third diameter less than the first and second diameters.

A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.

A method for producing a 3D memory device, the method including: providing a first level including a first single crystal layer and control circuits; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; forming at least one third level above the at least one second level; performing a second etch step including etching holes within the third level; and performing additional processing steps to form a plurality of first memory cells within the second level and a plurality of second memory cells within the third level, where each of the first memory cells include one first transistor, where each of the second memory cells include one second transistor, where at least one of the first or second transistors has a channel, a source, and a drain having a same doping type.

A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.