A method of fabricating a semiconductor structure includes the following steps. A first dummy gate structure and a second dummy gate structure are formed on a semiconductor substrate. A recess is formed next to the first and the second dummy gate structure and in the semiconductor substrate. A pair of first spacers is formed adjacent to the first dummy gate structure. A pair of second spacers is formed adjacent to the second dummy gate structure. One of the first spacers extends from a first sidewall of the first dummy gate structure to a first inner sidewall of the recess. One of the second spacers extends from a second sidewall of the second dummy gate structure to a second inner sidewall of the recess. A first isolation layer is formed on a bottom surface of the recess. A first conducting layer is formed on the first isolation layer.

Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed.

A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

This invention provides a semiconductor device with high speed operation and reduced size. A circuit includes a circuit including a memory circuit and a circuit including a logic circuit; thus, the circuit functions as a memory device having a function of storing data and a function of performing logic operation. The circuit can output, in addition to data stored in the circuit, data corresponding to a result of logic operation performed using data stored in the circuit as an input signal. The circuit can directly obtain a result of logic operation from the circuit, and thus, the frequency of input/output of a signal performed between the circuit and the circuit can be reduced.

A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc<tm.

An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(π/4).

According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third interconnects; a fourth interconnect; a semiconductor member; a charge storage member; and a conductive member. One of the plurality of third interconnects is disposed on two second-direction sides of the conductive member. Portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member are formed as one body.

A non-volatile memory device includes a semiconductor substrate and a tunnel insulating layer and a gate electrode. A multiple tunnel insulation layer with a plurality of layers, a charge storage insulation layer, and a multiple blocking insulation layer with layers are sequentially stacked between the gate electrode and the tunnel insulating layer. A first diffusion region and a second diffusion region in the semiconductor substrate are adjacent to opposite respective sides of the gate electrode. When a voltage is applied to the gate electrode and the semiconductor substrate to form a voltage level difference therebetween, a minimum field in the tunnel insulation layer is stronger than in the blocking insulation layer. A minimum field at a blocking insulation layer can be stronger than at a tunnel insulation layer, and the migration probability of charges through the tunnel insulation layer can be higher than through the blocking insulation layer.

The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.