A superconducting qubit is manufactured by stacking up atomically-thin, crystalline monolayers to form a heterostructure held together by van der Waals forces. Two sheets of superconducting material are separated by a third, thin sheet of dielectric to provide both a parallel plate shunting capacitor and a Josephson tunneling barrier. The superconducting material may be a transition metal dichalcogenide (TMD), such as niobium disilicate, and the dielectric may be hexagonal boron nitride. The qubit is etched, or material otherwise removed, to form a magnetic flux loop for tuning. The heterostructure may be protected by adhering additional layers of the dielectric or other insulator on its top and bottom. For readout, the qubit may be coupled to an external resonator, or the resonator may be integral with one of the sheets of superconducting material.

Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.

In an embodiment, a quantum device includes a first set of protrusions formed on a substrate and a second set of protrusions formed on a qubit chip. In the embodiment, the quantum device includes a set of bumps formed on an interposer, the set of bumps formed of a material having above a threshold ductility at a room temperature range, wherein a first subset of the set of bumps is configured to cold weld to the first set of protrusions and a second subset of the set of bumps is configured to cold weld to the second set of protrusions.

A resistive component in a hybrid microwave attenuator circuit is configured to attenuate a plurality of frequencies in an input signal. The hybrid microwave attenuator circuit is further configured with a dispersive component to attenuate a second plurality of frequencies within a frequency range by reflecting off portions of the input signal at those frequencies that are within the frequency range. The resistive component and the dispersive component are arranged in a series configuration relative to one another in the hybrid microwave attenuator circuit.

The present invention provides a sensor and measuring method. The sensor comprises multiple-layer organo-metallic cross-linked polymers forming various superlattice nanostructured biomimetic membranes for sensing Cooper-pair wave transmissions causing intrinsic magnetic flux quantum observed based on a Josephson junction toroidal array and a controllable state-switch valve having a double-pole electron-relay that promoted Cooper pairs coherently transmitting waves in the membranes within and cross the Josephson toroidal junction barriers at zero-bias. The One-Device-Assembly system enables a femto-joule energy consumption for quantum qubits; or acting as an energy storage device that stores energy 1.53 MJ/cm.sup.2 for an application in automobile vehicles.

Materials and methods are disclosed for fabricating superconducting integrated circuits for quantum computing at millikelvin temperatures, comprising both quantum circuits and classical control circuits, which may be located on the same integrated circuit or on different chips of a multi-chip module. The materials may include components that reduce defect densities and increase quantum coherence times. Multilayer fabrication techniques provide low-power and a path to large scale computing systems. An integrated circuit system for quantum computing is provided, comprising: a substrate; a kinetic inductance layer having a kinetic inductance of at least 5 pH/square; a plurality of stacked planarized superconducting layers and intervening insulating layers, formed into a plurality of Josephson junctions having a critical current of less than 100 μA/μm.sup.2; and a resistive layer that remains non-superconducting at a temperature below 1 K, configured to damp the plurality of Josephson junctions.

Systems and methods for determining critical timing paths in a superconducting circuit design including Josephson junctions are provided. An example method includes providing timing information concerning a plurality of source terminals of at least one logic gate coupled with a first sink terminal of the at least one logic gate. The method further includes using a processor, determining whether, in view of the timing information, the first sink terminal is reachable by a single flux quantum (SFQ) pulse within a predetermined range of arrival time based on an assigned first phase to the at least one logic gate.

A device includes: a substrate; a superconducting quantum interference device (SQUID) including a superconductor trace arranged on an upper surface of the substrate and having at least one Josephson junction interrupting a path of the superconductor trace, in which the superconductor trace includes a first superconductor material that exhibits superconducting properties at or below a corresponding superconducting critical temperature; and a dielectric capping layer on an upper surface of the SQUID, in which the dielectric capping layer covers a majority of the superconductor trace of the SQUID, and the capping layer includes an opening through which a first region of the SQUID is exposed, the first region of the SQUID including a first Josephson junction.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a gate disposed on a quantum well stack; an insulating material disposed on the gate; and a conductive via extending through the insulating material and in conductive contact with the gate.

A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.