Circuits and methods related to temperature sensing of regions within a superconducting integrated circuit (IC) using in-situ resonators are described. An example relates to a superconducting IC including a first resonator having a first spatial location in relation to a floor plan of the superconducting IC. The superconducting IC further includes a second resonator having a second spatial location in relation to the floor plan of the superconducting IC. The superconducting IC further includes a feed line configured to provide a test signal to each of the first resonator and the second resonator in order to elicit a frequency response from the first resonator or the second resonator, where the frequency response is correlated with a first region within the superconducting IC corresponding to the first spatial location or with a second region within the superconducting IC corresponding to the second spatial location.

A superconducting quantum circuit includes a plurality of SQUIDs (Superconducting Quantum Interference Devices) connected in parallel, each of the plurality of SQUIDs including a first superconducting line, a first Josephson junction, a second superconducting line, and a second Josephson junction connected in a loop, wherein a junction area of the first Josephson junction and a junction area of the second Josephson junction are different from each other, the plurality of SQUIDs configured to be mutually different in either one or both of: a sum of the junction area of the first Josephson junction and the junction area of the second Josephson junction; and a ratio of the junction area of the first Josephson junction to the junction area of the second Josephson junction.

A superconducting memory cell includes a magnetic Josephson junction (MJJ) with a ferromagnetic material, having at least two switchable states of magnetization. The binary state of the MJJ manifests itself as a pulse appearing, or not appearing, on the output. A superconducting memory includes an array of memory cells. Each memory cell includes a comparator with at least one MJJ. Selected X and Y-directional write lines in their combination are capable of switching the magnetization of the MJJ. A superconducting device includes a first and a second junction in a stacked configuration. The first junction has an insulating layer barrier, and the second junction has an insulating layer sandwiched in-between two ferromagnetic layers as barrier. An electrical signal inputted across the first junction is amplified across the second junction.

High-saturation power Josephson ring modulators and fabrication of the same are provided. A Josephson ring modulator can comprise a plurality of matrix junctions. Matrix junctions of the plurality of matrix junctions can comprise respective superconducting parallel branches that can comprise a plurality of Josephson junctions operatively coupled in a series configuration. A method can comprise forming a first matrix junction comprising arranging a first group of Josephson junctions as first parallel branches. The method can also comprise forming a second matrix junction comprising arranging a second group of Josephson junctions as second parallel branches. Further, the method can comprise forming a third matrix junction comprising arranging a third group of Josephson junctions as third parallel branches. In addition, the method can comprise forming a fourth matrix junction comprising arranging a fourth group of Josephson junctions as fourth parallel branches.

Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

A method of fabricating a superconductor device includes providing a first metal layer on top of the substrate. An oxidation of a top surface of the first metal layer is rejected. A second metal layer is deposited on top of the second metal layer. A superconducting alloy of the first metal layer and the second metal layer is created between the first metal layer and the second metal layer. There is no oxide layer between the superconducting alloy and the first metal layer.

An integrated circuit is provided that comprises a first substrate having a plurality of conductive contact pads spaced apart from one another on a surface of the first substrate, a dielectric layer overlying the first substrate and the plurality of conductive contact pads, and a second substrate overlying the dielectric layer. A plurality of superconducting contacts extend through the second substrate and the dielectric layer to the first substrate, wherein each superconducting contact of the plurality of superconducting contacts is aligned with and in contact with a respective conductive contact pad of the plurality of conductive contact pads.

Lattice arrangements for quantum qubits are described. A lattice arrangement can comprise adjacent structures having vertices connected by edges. The qubits can be positioned on the vertices. A qubit in the lattice arrangement directly connects to not more than three other qubits, or connects to another qubit via a coupling qubit on an edge between two qubits on a vertex. The adjacent structures can comprise hexagons, dodecagons or octagons. A superconducting qubit lattice can comprise superconducting target qubits and superconducting control qubits. The superconducting qubit lattice can comprise adjacent structures having vertices connected by edges, with target qubits positioned on the vertices and control qubits positioned on the edges. Logic operations between adjacent superconducting target and control qubits can be implemented by driving the superconducting control qubit at or near the frequency of the superconducting target qubit.

A superconducting circuit includes a Josephson junction device including a lower superconducting material layer formed on a substrate and a junction layer formed on the lower superconducting material layer. The superconducting circuit also includes an upper superconducting material layer formed over the junction layer. At least the lower superconducting material layer comprises grains having a size that is larger than a size of the Josephson junction.

An apparatus and a method for indirectly cooling a superconducting quantum interference device (SQUID) are provided. The apparatus includes an outer container extending in a vertical direction; a metallic inner container inserted into the outer container to store a liquid coolant, the metal inner container including a top plate; a SQUID sensor module disposed between a bottom surface of the outer container and a bottom surface of the inner container; a heat transfer pillar adapted to cool the SQUID sensor module, the heat transfer pillar having one end connected to the bottom surface of the inner container and the other end directly or indirectly connected to the SQUID sensor module; a magnetic shield part formed of a superconductor covering a top surface of the SQUID sensor module; and a heat conduction plate being in thermal contact with the other end of the heat transfer pillar.