A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main surface of a semiconductor substrate; a reference potential wire coupled with the p type well layer, and extending in the X direction; first and second active regions arranged on the opposite sides of the reference potential wire in the Y direction; and a gate electrode layer extending in the Y direction in such a manner as to cross with the first and second active regions. Then, the gate electrode layer has a first gate electrode of a second conductivity type at the crossing part with the first active region, a second gate electrode of the second conductivity type at the crossing part with the second active region, and a non-doped electrode between the first gate electrode and the second gate electrode.

Structures for a ferroelectric capacitive memory device and methods of forming a structure for a ferroelectric capacitive memory device. The structure comprises a first electrode including a first doped region in a semiconductor layer and a second doped region in the semiconductor layer, an interconnection that is configured to connect the first doped region to the second doped region, a ferroelectric layer on the semiconductor layer, and a second electrode including a first section and a second section on the ferroelectric layer. The first section of the second electrode comprises a first material with a first work function, and the second section of the second electrode comprises a second material with a second work function that is greater than the first work function of the first material.

A semiconductor device according to the present disclosure, includes a semiconductor substrate; a gate electrode which is provided above the semiconductor substrate with a gate insulating film intervening between the gate electrode and the semiconductor substrate and is made with polysilicon; a first metal layer which is provided on the gate electrode; a second metal layer which is provided on the first metal layer; a first electrode which is provided above the second metal layer with an interlayer insulating film intervening between the first electrode and the second metal layer; and a second electrode which is provided on an opposite side of the semiconductor substrate from the first electrode, wherein at least one of the first metal layer and the second metal layer contains a metal which suppresses movement of a movable ion.

A semiconductor device includes a first region that contains a first conductive type impurity and is provided on a substrate, a second region that is provided in the first region and contains the first conductive type impurity at a higher concentration than the first region, a first structure that is provided on the substrate on one side of the second region in a first direction along the substrate and has a first sidewall at least on the second region side, a second structure that is provided on the substrate on the other side of the second region in the first direction and has a second sidewall at least on the second region side, and a contact that passes between the first and second sidewalls facing each other across the second region, extends to the second region, and is electrically connected to the second region.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

A semiconductor device includes a trench formed in a substrate; a first gate filled in a lower portion of the trench; and a second gate disposed over the first gate, wherein each of the first gate and the second gate contains oxygen material, and an oxygen content of the first gate is greater than an oxygen content of the second gate.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

Some embodiments of the disclosure provide an apparatus comprising a cell contact coupled to a memory cell capacitor. The cell contact includes a contact metal and a barrier film at least on a side surface of the contact metal. A lower portion of the barrier film comprises a barrier metal. An upper portion of the barrier film comprises an insulating film.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).