Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).

Claims

1. A method of manufacturing a semiconductor device comprising the steps of: (a) preparing a semiconductor substrate having an upper surface and a lower surface; (b) after the step (a), forming a first insulating film extending from an upper surface of the semiconductor substrate to an inside of the semiconductor substrate; (c) after the step (b), forming a second insulating film having a thickness thinner than the first insulating film on the first insulating film; (d) after the step (c), forming a first conductive film on the second insulating film; (e) after the step (d), forming an interlayer insulating film on the upper surface of the semiconductor substrate so as to cover the first conductive film; (f) after the step (e), forming a first contact hole in the interlayer insulating film, the first conductive film, the second insulating film and the first insulating film so that a bottom portion of the first contact hole is located in the first insulating film, (g) after the step (f), subjecting the interlayer insulating film, the second insulating film and the first insulating film to an isotropic etching treatment, and (h) after the step (g), embedding a first plug in the first contact hole, wherein a side surface of the interlayer insulating film is separated from a side surface of the first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film in the first contact hole by the isotropic etching treatment in the step (g), wherein a side surface of the first insulating film and a side surface of the second insulating film in the first contact hole are separated from the side surface of the first conductive film so that a part of a lower surface of the first conductive film is exposed from the first and second insulating films by the isotropic etching treatment in the step (g), and wherein a first distance from the lower surface of the first conductive film to the bottom portion of the first contact hole is longer than a second distance from the side surface of the first conductive film to the side surface of the interlayer insulating film.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the first plug includes a barrier metal film and a second conductive film, wherein the step (h) includes: (h1) forming the barrier metal film in the first contact hole by CVD method; and (h2) forming the first conductive film on the barrier metal film so as to fill the first contact hole, and wherein the barrier metal film is in contact with a portion of the upper surface, the side surface and a portion of a lower surface of the first conductive film in the first contact hole.

3. A method of manufacturing a semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film formed by a thermal oxidation method, the second insulating film is a silicon oxide film formed by a CVD method, and the first conductive film is a polycrystalline silicon film formed by a CVD method.

4. A method of manufacturing a semiconductor device according to claim 3, wherein the first insulating film is formed to a position higher than the upper surface of the semiconductor substrate in the step (b), wherein an isotropic etching process is performed on the first insulating film so that a thickness of the first insulating film is reduced between the step (b) and the step (c).

5. A method of manufacturing the semiconductor device according to claim 1, further comprising the step of forming an IGBT cell in a region different from a region in which the first conductive film is formed, wherein the step of forming the IGBT cell includes: (i) forming a trench in the upper side of the semiconductor substrate, after the step (b) and before the step (c); (j) forming a gate insulating film in the trench, after the step (i) and before the step (c); (k) forming a gate electrode on the gate insulating film to fill up the trench, after the step (j) and before the step (c); (l) forming a base region of a first conductivity type on the upper surface of the semiconductor substrate so that a bottom portion of the base region is located above a bottom portion of the trench, after the step (d) and before the step (e), and (m) forming an emitter region of a second conductivity type opposite to the first conductivity type in the base region, after the step (l) and before the step (e), wherein a portion of the interlayer insulating film is formed to cover the gate electrode, the base region and the emitter region in the step (e), wherein a second contact hole is formed in the portion of the interlayer insulating film so that a bottom portion thereof is located in the base region in the step (f), wherein a side surface of the portion of the interlayer insulating film is separated from a side surface of the emitter region so that a part of an upper surface of the emitter region is exposed from the portion of the interlayer insulating film by the step (g), and wherein a second plug is embedded in the second contact hole in the step (h).

6. A method of manufacturing a semiconductor device according to claim 5, further comprising the steps of: (n) performing a planarizing process on the interlayer insulating film by a CMP method in order to planarize an upper surface of the interlayer insulating film, after the step (e) and before the step (f).

7. A method of manufacturing a semiconductor device according to claim 5, further comprising the step of: (o) forming a gate wiring electrically connected to the gate electrode on the interlayer insulating film and forming an emitter electrode on the interlayer insulating film region, after the step (h), wherein the base region and the emitter region are electrically connected to the emitter electrode via the second plug, and wherein the first conductive film is electrically connected to the gate wiring via the first plug and is used as one of a resistive element or a diode element.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a plan view showing the entire semiconductor device of the first embodiment.

(2) FIG. 2 is a plan view showing a semiconductor device according to the first embodiment.

(3) FIG. 3 is a plan view showing a semiconductor device according to the first embodiment.

(4) FIG. 4 is a plan view showing a semiconductor device according to the first embodiment.

(5) FIG. 5 is a sectional view showing a semiconductor device according to the first embodiment.

(6) FIG. 6 is a sectional view showing a semiconductor device according to the first embodiment.

(7) FIG. 7 is an enlarged cross-sectional view of a part of a semiconductor device according to a first embodiment.

(8) FIG. 8 is an enlarged cross-sectional view of a part of a semiconductor device according to the first embodiment.

(9) FIG. 9 is a cross-sectional view showing a manufacturing process of a semiconductor device according to the first embodiment.

(10) FIG. 10 is a cross-sectional view illustrating a manufacturing process following FIG. 9.

(11) FIG. 11 is a cross-sectional view illustrating a manufacturing step following FIG. 10.

(12) FIG. 12 is a cross-sectional view illustrating a manufacturing step following FIG. 11.

(13) FIG. 13 is a cross-sectional view illustrating a manufacturing step following FIG. 12.

(14) FIG. 14 is a cross-sectional view illustrating a manufacturing step following FIG. 13.

(15) FIG. 15 is a cross-sectional view illustrating a manufacturing step following FIG. 14.

(16) FIG. 16 is a cross-sectional view illustrating a manufacturing step following FIG. 15.

(17) FIG. 17 is a cross-sectional view illustrating a manufacturing step following FIG. 16.

(18) FIG. 18 is a cross-sectional view illustrating a manufacturing step following FIG. 17.

(19) FIG. 19 is a cross-sectional view illustrating a manufacturing step following FIG. 18.

(20) FIG. 20 is a cross-sectional view illustrating a manufacturing step following FIG. 19.

(21) FIG. 21 is a cross-sectional view illustrating a manufacturing step following FIG. 20.

(22) FIG. 22 is a cross-sectional view illustrating a manufacturing step following FIG. 21.

(23) FIG. 23 is a cross-sectional view illustrating a manufacturing step following FIG. 22.

(24) FIG. 24 is a cross-sectional view illustrating a manufacturing step following FIG. 23.

(25) FIG. 25 is a cross-sectional view illustrating a manufacturing step following FIG. 24.

(26) FIG. 26 is a cross-sectional view illustrating a manufacturing step following FIG. 25.

(27) FIG. 27 is a cross-sectional view showing a semiconductor device according to a first study example.

(28) FIG. 28 is a cross-sectional view showing a semiconductor device according to a second study example.

(29) FIG. 29 is a cross-sectional view showing a semiconductor device according to a third study example.

(30) FIG. 30 is a cross-sectional view illustrating a manufacturing process following FIG. 29.

(31) FIG. 31 is A cross-sectional view illustrating a manufacturing process following FIG. 30.

(32) FIG. 32 is a cross-sectional view illustrating a manufacturing process following FIG. 31.

DETAILED DESCRIPTION

(33) Hereinafter, embodiments will be described in detail based on the drawings. In all the drawings for explaining the embodiments, members having the same functions are denoted by the same reference numerals, and repetitive descriptions thereof are omitted. In the following embodiments, descriptions of the same or similar parts will not be repeated in principle except when particularly necessary.

(34) A semiconductor device 100 according to Embodiment 1 will be described below with reference to FIG. 1 to FIG. 8. FIG. 1 is a plan view illustrating a semiconductor chip that is a semiconductor device 100.

(35) As shown in FIG. 1, most of the device 100 is covered with an emitter electrode EE, and a plurality of cells constituting a IGBT are formed under the emitter electrode EE. A gate-line GW is formed around the emitter-electrode EE. A central portion of the emitter-electrode EE serves as an emitter pad, and a central portion of the gate wire serves as a gate pad. External connection terminals such as wire bonding or clips (copper plates) are connected to the emitter pad and the gate pad, so that the semiconductor device 100 is electrically connected to another semiconductor chip, a wiring board, or the like.

(36) The device 100 includes regions 1A3A that are regions that differ from each other. The region 1A in FIG. 1 is a resistance element region in which a resistance element is formed. The resistive element is used for a gate resistor or the like. The region 2A in FIG. 1 is a cell region in which a plurality of cells constituting a IGBT are formed. The region 3A in FIG. 1 is a diode element region in which a diode element is formed. Diode elements are used for gate protection or temperature sensing, etc.

(37) FIG. 2 is a plan view of a main part corresponding to the region 1A. FIG. 3 is a plan view of a main part corresponding to the region 3A. FIG. 4 is a plan view of a main part corresponding to the region 2A. FIG. 5 is a cross-sectional view taken along A-A line of FIG. 2 and a cross-sectional view taken along B-B line of FIG. 4; FIG. 6 is a cross-sectional view taken along C C line of FIG. 3.

(38) As shown in FIGS. 2 to 4, the contact hole CH1, CH2 has a slit-shape in which an opening width in a first direction is wider than an opening width in a second direction perpendicular to the first direction in a plan view. That is, the contact hole CH1, CH2 has a rectangular shape in plan view.

(39) However, the planar shape of the contact hole CH1, CH2 is not limited to the slit shape, and may be a dot shape in which the opening width in the first direction is the same as the opening width in the second direction. That is, a plurality of contact holes CH1, CH2 having a rectangular shape in a plan view may be arranged in the first direction.

(40) In many cases, the planar shape of the contact hole CH1, CH2 is a shape in which the corners are rounded after resolution of photolithography. Therefore, finally, the contact hole CH1, CH2 has a shape in which the corners of the rectangle are rounded or a circular shape in a plan view.

(41) The main features of the diode element shown in FIGS. 3 and 6 are substantially the same as the main features of the resistor element shown in FIGS. 2 and 5, except that a p-type anode region PLP and an n-type cathode region PLN are formed on the conductive film PL. Therefore, the resistive elements in the region LA and the cells in IGBT of the region 2A will be described below.

(42) As illustrated in FIGS. 5 and 6, the semiconductor device 100 includes a semiconductor board SUB having a low-concentration n-type drift-region NV. Here, the n-type semiconductor-substrate SUB itself constitute the drift-region NV. Note that the drift-region NV may be a stack of an n-type silicon substrate and semiconductor layers grown by introducing phosphorus (P) onto the silicon substrate by an epitaxial growth method. In the present application, such a stack is also described as being a semiconductor-substrate SUB.

(43) On the lower surface of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS is formed on the semiconductor substrate SUB. The field stop region NS is provided to prevent the depletion layer extending from pn junction on the upper surface of SUB from reaching the p-type collector region PC when IGBT is turned off.

(44) On the lower surface of the semiconductor substrate SUB, a p-type collector region (impurity region) PC is formed on the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

(45) A collector-electrode CE is formed under the lower surface of the semiconductor-substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies a collector potential to the collector region PC. The collector electrode CE consists of metallic films such as AlSi films, Ti films, NiV films and Au films.

(46) The configuration of the region LA will be described below. In the device 100, a conductive film PL formed on the region 1A is used as a resistive element.

(47) As shown in FIG. 5, a p-type well area PW is formed in the semiconductor substrate SUB on the upper surface of the semiconductor substrate SUB. The well region PW is formed in the same process as the floating region PF of the region 1A, but is physically separated from the floating region PF.

(48) Insulating layers IFL are formed from the upper surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB. In other words, in the semiconductor substrate SUB, the insulating layer IFL is formed, and the lower surface of the insulating layer IFL is located below the upper surface of the semiconductor substrate SUB.

(49) The insulating layers IFL include an insulating film IF1 and an insulating film IF2. The insulating film IF1 is formed inside the semiconductor-substrate SUB and is, for example, a silicon-oxide film. The insulating film IF2 is formed on the insulating film IF1, and is, for example, a silicon-oxide film. The insulating film IF2 has a thickness smaller than that of the insulating film IF1. The thickness of the insulating film IF1 is, for example, 500600 nm. The thickness of the insulating film IF2 is, for example, 50100 nm.

(50) A conductive film PL is formed on the insulating layers IFL. The conductive film PL is, for example, a p-type doped polysilicon film. The thickness of the conductive film PL is, for example, 150250 nm.

(51) An interlayer insulating film IL is formed on the upper surface of the semiconductor-substrate SUB so as to cover the conductive film PL. The interlayer insulating film IL is, for example, a silicon-oxide film. Further, the interlayer insulating film IL is subjected to a planarization treatment for planarizing the upper surface of the interlayer insulating film IL. Therefore, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor-substrate SUB is, for example, 600800 nm, but the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300450 nm.

(52) Contact holes CH1 are formed in the interlayer insulating film IL, the conductive film PL, and the insulating layer IFL. The bottom of the contact hole CH1 is located in the insulating layers IFL (in the insulating film IF1). A plug-in PG1 is embedded in the contact hole CH1. The plug PG1 includes a barrier metal film BM and a conductive film CF formed on the barrier metal film BM. The barrier metal film BM is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film CF is, for example, a tungsten film.

(53) A gate wire GW is formed on the interlayer insulating film IL. The conductive film PL is electrically connected to the gate-line GW via a plug PG1. The conductive film PL can be used as a gate resistor by forming an electric path in the middle of the gate wire GW by the conductive film PL.

(54) A main feature of the first embodiment is the shape of the contact hole CH1 and the point where the plug PG1 and the conductive film PL are in contact with each other in the contact hole CH1.

(55) <Structure of IGBT cell> The structure of the region 2A is described below. Here, a IGBT in which a vertical trench gate structure is applied will be exemplified.

(56) As shown in FIG. 5, a trench TR is formed in the semiconductor substrate SUB on the upper surface of the semiconductor substrate SUB. The depth of the trench TR is, for example, 3 to 4 micrometers. A gate insulating film GI is formed in the trench TR. The gate electrode GE is formed on the gate insulating film GI so as to fill the trench TR. The gate insulating film GI is, for example, a silicon oxide film, and the gate electrode GE is, for example, a polycrystalline silicon film into which an n-type impurity is introduced.

(57) On the upper surface of the semiconductor substrate SUB, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between the pair of gate-electrode GE. A p-type base region (impurity region) PB is formed in the hole barrier region NHB. An n-type emitter region (impurity region) NE is formed in the p-type base region PB. The bottom of the base region PB is located above the bottom of the trench TR, and the bottom of the emitter region NE is located above the bottom of the base region PB.

(58) Further, on the upper surface of the semiconductor substrate SUB, a p-type floating region (impurity region) PF is formed on the semiconductor substrate SUB other than the region where the hole barrier region NHB is formed. A p-type base region PB is formed in the floating region PF. The floating area PF is formed to a position deeper than the bottom of the trench TR in order to enhance the high breakdown voltage property, and is formed so as to cover the bottom of the trench TR.

(59) The interlayer insulating film IL is also formed on the upper surface of the semiconductor-substrate SUB in the region 2A so as to cover the gate-electrode GE, the emitter region NE, and the base region PB. Contact holes CH2 are formed in the interlayer insulating film IL, the emitter region NE, and the base region PB in the region 2A. The bottom of the contact hole CH2 is located in the base-region PB. A plug-in PG2 is embedded in the contact hole CH2. The plug PG2 is configured similarly to the plug PG1 and includes a barrier metal film BM and a conductive film CF.

(60) A p-type high-concentration diffused region (impurity region) PR is formed in the base region PB around the bottom portion of the contact hole CH2. The high-concentration diffused area PR is provided to reduce the contact-resistance with the plug PG2 and to prevent latch-up.

(61) In the region 2A, since an isotropic etch process is performed on the interlayer insulating film IL in order to increase the contact area between the plug PG2 embedded in the contact hole CH2 and the emitter region NE, the side surface of the interlayer insulating film IL is retracted. That is, in the contact hole CH2, the side surface of the interlayer insulating film IL is separated from the side surface of the emitter region NE so that a part of the upper surface of the emitter region NE is exposed.

(62) An emitter-electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, and the highly diffused region PR via the plug PG2, and supplies an emitter potential to these regions. Although not illustrated here, the gate interconnect GW is electrically connected to the gate electrode GE via other plug, and supplies a gate potential to the gate electrode GE.

(63) The emitter-electrode EE and the gate-line GW are formed of, for example, a TiW film and an aluminium film formed on TiW film. The aluminum film is a main conductive film of the emitter-electrode EE and the gate-line GW, and is sufficiently thicker than TiW film.

(64) As shown in FIG. 6, the structure of the region 3A will be described below. In the device 100, a conductive film PL formed on the region 3A is used as a diode-element. Since the rest of the structure is the same as the region 1A, the explanation thereof will be omitted.

(65) In the diode device shown in FIG. 6, the p-type anode region PLP and the n-type cathode region PLN are formed by ion-implantation on the conductive film PL. Contact holes CH1 are formed in the anode region PLP and the cathode region PLN, respectively, and a plug PG1 is embedded in the contact hole CH1. Although not illustrated here, the emitter-electrode EE and the gate-line GW are formed on the interlayer insulating film IL in the region 3A. The anode region PLP is electrically connected to the emitter electrode EE via the plug PG1, and the cathode region PLN is electrically connected to the gate wire GW via the plug PG1.

(66) <Main features of the first embodiment> The main features of the first embodiment will be described with reference to FIGS. 7 and 8 below. FIG. 7 and FIG. 8 are enlarged cross-sectional views of the periphery of the contact hole CH1. FIG. 7 shows a state in which the plug PG1 is not embedded in the contact hole CH1.

(67) In the region 1A, since the isotropic etch process is performed on the interlayer insulating film IL in the same step as the step of forming the contact hole CH2 in the area 2A, the side surface of the interlayer insulating film IL is retreated.

(68) In the contact hole CH1, the side surface of the interlayer insulating film IL is separated from the side surface of the conductive film PL so that a part of the upper surface of the conductive film PL is exposed. The distance L2 between these sides is, for example, 50100 nm.

(69) Here, the insulating layers IFL are also retreated by the isotropic etching process described above. Therefore, in the contact hole CH1, the side surface (the side surface of the insulating film IF1 and the side surface of the insulating film IF2) of the insulating layer IFL is separated from the side surface of the conductive film PL so that a part of the lower surface of the conductive film PL is exposed. In other words, the opening width of the contact hole CH1 formed in the interlayer insulating film IL and the opening width of the contact hole CH1 formed in the insulating layer IFL are wider than the opening width of the contact hole CH1 formed in the conductive film PL.

(70) As will be described later, in the first embodiment, the contact hole CH1 is formed in advance so that the bottom of the contact hole CH1 reaches the inside of the insulating layers IFL prior to the isotropic etch process described above. Since the above-described isotropic etch process is performed in this condition, the distance L1 from the lower surface of the conductive film PL to the bottom portion of the contact hole CH1 is longer than the distance L3 of the third study example, and is longer than the distance L2. The distance L1 is, for example, a 150200 nm.

(71) In Study Example 3, since the distance L3 is short, a portion where the thickness of the barrier metal film BM is insufficient is likely to be generated. Therefore, in a portion where the barrier metal film BM is thin, it is difficult for the conductive film CF to grow sufficiently, and a gap is easily generated in the contact hole CH1, and there is a problem that WF.sub.6 gases react with the conductive film CF and a part of the conductive film CF is lacking.

(72) In the first embodiment, since the distance L1 is sufficiently long, the gases used in CVD method when forming the barrier metal film BM are sufficiently supplied to the vicinity of the lower surface of the conductive film PL. Therefore, a sufficiently thick barrier metal film BM is ensured in the contact hole CH1. Since the barrier metal film BM also serves as a seeding film when forming the conductive film CF, the conductive film CF is also sufficiently grown. Therefore, in the first embodiment, various problems that have occurred in the examination example 3 are solved, so that the reliability of the semiconductor device can be improved.

(73) The barrier metal film BM is in contact with a part of the upper surface of the conductive film PL, a side surface of the conductive film PL, and a part of the lower surface of the conductive film PL in the contact hole CH1. Therefore, since the contact area between the plug PG1 and the conductive film PL can be increased, the contact resistivity between the plug PG1 and the conductive film PL can be reduced, and the adhesion between the plug PG1 and the conductive film PL can be improved.

(74) Note that the same advantages as those of the resistive element of the region LA can be obtained also in the diode element of the region 3A.

(75) A method of manufacturing the semiconductor device 100 according to the first embodiment will be described below with reference to FIGS. 9 to 26.

(76) First, as shown in FIG. 9, a semiconductor-substrate SUB having an n-type drift-region NV is prepared. The semiconductor-substrate SUB has an upper surface and a lower surface. Next, the silicon oxide film 10 is formed on the upper surface of the semiconductor-substrate SUB by, for example, thermal oxidation. Next, a silicon nitride film 11 is formed on the silicon oxide film 10 by, for example, a CVD method.

(77) Next, as shown in FIG. 10, the silicon nitride film 11 and the silicon oxide film 10 in the region 1A are selectively removed by a photolithography technique and a dry etching process, and openings are formed in the silicon nitride film 11 and the silicon oxide film 10. Then, a portion of the semiconductor substrate SUB exposed at the opening is etched to form a trench in the semiconductor substrate SUB.

(78) Next, as shown in FIG. 11, the semiconductor substrate SUB is thermally oxidized to form an insulating film IF1 from the upper surface of the semiconductor substrate SUB to the inside of the semiconductor substrate SUB. In this state, the insulating film IF1 is formed to a position higher than the upper surface of the semiconductor-substrate SUB. That is, a LOCOS insulating film IF1 is formed on SUB of the region 1A. In this condition, the thickness of the insulating film IF1 is, for example, 700800 nm.

(79) Next, as shown in FIG. 12, the silicon nitride film 11 is removed by an isotropic etching process using a solution containing phosphoric acid. Next, a p-type well region PW is formed on the semiconductor substrate SUB of the region LA by photolithography and ion implantation, and a p-type floating region PF is formed on the semiconductor substrate SUB of the region 2A. Next, an n-type hole-barrier region NHB is formed on SUB of the region 2A by photolithography and ion-implantation.

(80) Next, as shown in FIG. 13, a trench TR is formed in SUB of the region 2A by a photolithography technique and a dry etching process.

(81) Next, as shown in FIG. 14, the silicon oxide film 10 is removed by an isotropic etching process using a solution containing hydrofluoric acid. At this time, since the insulating film IF1 is also exposed to the isotropic etching treatment, the upper surface of the insulating film IF1 is retreated, and the thickness of the insulating film IF1 is reduced.

(82) Next, as shown in FIG. 15, the semiconductor-substrate SUB is subjected to a heat treatment at, for example, 1000 to 1200 C. to diffuse impurities contained in the hole barrier region NHB, the floating region PF, and the well region PW. By this heat treatment, the hole barrier region NHB diffuses to the vicinity of the bottom of the trench TR, and the floating region PF diffuses to a position deeper than the bottom of the trench TR so as to cover the bottom of the trench TR.

(83) Although not shown, this heat treatment is performed with a sacrificial silicon oxide film formed on the semiconductor-substrate SUB including the inside of the trench TR. After the heat treatment, the sacrificial silicon oxide film is removed by an isotropic etching process using a solution containing hydrofluoric acid. At this time, since the insulating film IF1 is also exposed to the isotropic etching treatment, the upper surface of the insulating film IF1 is retreated, and the thickness of the insulating film IF1 is reduced. In this condition, the thickness of the insulating film IF1 is, for example, 500600 nm.

(84) Next, as shown in FIG. 16, a gate-insulating film GI is formed inside the trench TR and on the semiconductor-substrate SUB. The gate-insulating film GI is formed by a thermal oxidation treatment. The thickness of the gate dielectric film GI is, for example, 100 nm.

(85) Next, the gate-electrode GE is formed so as to fill the trench TR. In order to form the gate electrode GE, first, an n-type doped polycrystalline silicon film is formed on the gate insulating film GI by, for example, a CVD method. Next, the polycrystalline silicon film formed outside the trench TR is removed by dry-etching. A polysilicon film formed inside the trench TR is left as a gate-electrode GE.

(86) Next, as shown in FIG. 17, an insulating film IF2 is formed on the insulating film IF1, the gate electrode GE, and the gate insulating film GI formed outside the trench TR by, for example, a CVD method. The thickness of the insulating film IF2 is, for example, 50100 nm. Next, a conductive film PL is formed on the insulating film IF2 by, for example, a CVD method. The thickness of the conductive film PL is, for example, 150250 nm.

(87) Next, a p-type impurity is introduced into the conductive film PL by ion-implantation. Note that n-type and p-type impurities are introduced into the conductive film PL on the region 3A by a photolithography technique and an ion-implantation method, and the anode region PLP and the cathode region PLN are formed. Next, a resist pattern RP1 is formed on the conductive film PL on the region 1A so as to selectively cover the conductive film PL located on the insulating film IF1. Note that the anode region PLP and the cathode region PLN are also covered with the resist pattern RP1.

(88) Next, as shown in FIG. 18, the conductive film PL and the insulating film IF2 are patterned by performing a dry etching process using the resist pattern RP1 as a mask. As a result, a resistive element is formed in the region 1A, and a diode element is formed in the region 3A. The patterned insulating film IF2 and the insulating film IF1 constitute the insulating layers IFL. In this dry-etching process, the gate insulating film GI formed outside the trench TR is also removed. Thereafter, the resist pattern RP1 is removed by ashing.

(89) Next, as shown in FIG. 19, a p-type base region PB is formed on the semiconductor substrate SUB (the floating region PF and the hole barrier region NHB) by photolithography and ion implantation on the upper surface of the semiconductor substrate SUB. The bottom of the base-region PB is located above the bottom of the trench TR. Next, an n-type emitter region NE is formed in the base region PB by photolithography and ion-implantation. Thereafter, heat treatment is performed to activate impurities contained in the impurity regions.

(90) Next, as shown in FIG. 20, an interlayer insulating film IL is formed on the upper surfaces of the regions 1A and 2A of the semiconductor-substrate SUB so as to cover the conductive film PL, the gate-electrode GE, the base-region PB, and the emitter-region NE.

(91) Next, as shown in FIG. 21, in order to planarize the upper surface of the interlayer insulating film IL, a planarization process is performed by CMP method on the interlayer insulating film IL of the regions 1A and 2A. After the planarization treatment, the thickness of the interlayer insulating film IL on the upper surface of the semiconductor substrate SUB is, for example, 600800 nm, and the thickness of the interlayer insulating film IL on the upper surface of the conductive film PL is, for example, 300450 nm.

(92) Next, as shown in FIG. 22, a contact hole CH1 is formed in the interlayer insulating film IL, the conductive film PL, the insulating film IF2, and the insulating film IF1 in the region 1A by a photolithography technique and a dry etching process. At the same time, in the region 2A, a contact hole CH2 is formed in the interlayer insulating film IL, the emitter region NE, and the base region PB. Next, a p-type high-concentration diffused region PR is formed on the base region PB located at the bottom of the contact hole CH2 by ion-implantation.

(93) Here, the bottom of the contact hole CH1 is located in the insulating film IF1, and the bottom of the contact hole CH2 is located in the base-region PB. In Study 3, as shown in FIG. 29, the contact hole CH1 penetrated the conductive film PL, and the bottom portion of the contact hole CH1 was located on the insulating film IF2 or in the insulating film IF2. In the first embodiment, the contact hole CH1 is formed deeper than in the third embodiment.

(94) At this point, the distance from the lower surface of the conductive film PL to the bottom portion of the contact hole CH1 is, for example, 100150 nm. In other words, the amount of etching the insulating layer IFL in FIG. 22 is set to be larger than the amount of etching the interlayer insulating film IL and the insulating layer IFL by the isotropic etching process in FIG. 23.

(95) Next, as shown in FIG. 23, the interlayer insulating film IL and the insulating layer IFL (the insulating film IF2 and the insulating film IF1) are isotropically etched using solutions containing hydrofluoric acid. By the isotropic etching process, the side surface of the interlayer insulating film IL is separated from the side surface of the conductive film PL so that a part of the upper surface of the conductive film PL is exposed in the contact hole CH1. Further, in the contact hole CH1, the side surface (the side surface of the insulating film IF1 and the side surface of the insulating film IF2) of the insulating layer IFL is separated from the side surface of the conductive film FL so that a part of the lower surface of the conductive film PL is exposed. Further, in the contact hole CH2, the side surface of the interlayer insulating film IL is separated from the side surface of the emitter region NE so that a part of the upper surface of the emitter region NE is exposed.

(96) Then, the depth of the contact hole CH1 is also increased by the isotropic etching process described above. That is, as shown in FIG. 7, the distance L1 from the lower surface of the conductive film PL to the bottom portion of the contact hole CH1 is longer than the distance L2.

(97) Next, as shown in FIG. 24, a barrier metal film BM is formed on the interlayer insulating film IL including the inside of the contact hole CH1 and the inside of the contact hole CH2 by CVD method. The barrier metal film BM is, for example, a laminated film of a titanium film and a titanium nitride film. At this point, the barrier metal film BM is in contact with a part of the upper surface of the conductive film PL, a side surface of the conductive film PL, and a part of the lower surface of the conductive film PL in the contact hole CH1.

(98) Next, a conductive film CF is formed on the barrier metal film BM so as to fill the inside of the contact hole CH1 and the inside of the contact hole CH2. The conductive film CF is, for example, a tungsten film, and is formed using WF.sub.6 gases.

(99) Next, as shown in FIG. 25, the conductive film PL and the barrier metal film BM formed outside the contact hole CH1 and outside the contact hole CH2 are removed by a polishing treatment or an anisotropic dry etching treatment using a CMP method. As a result, in the contact hole CH1, the conductive film PL and the barrier metal film BM are embedded in the plug PG1, and the conductive film PL and the barrier metal film BM are embedded in the contact hole CH2 in the plug PG2.

(100) Next, as shown in FIG. 26, a gate wire GW is formed on the interlayer insulating film IL of the region LA, and an emitter-electrode EE is formed on the interlayer insulating film IL of the region 2A. First, a TiW film is formed on the interlayer insulating film IL by, e.g., sputtering, and an aluminium film is formed on TiW film by, e.g., sputtering. Next, TiW film and the aluminium film are patterned by a photolithography technique and a dry etching process to form a gate-wiring GW and an emitter-electrode EE.

(101) Thereafter, the field stop region NS, the collector region PC, and the collector electrode CE are formed on the lower surface of the semiconductor-substrate SUB, thereby obtaining the structure of FIG. 5.

(102) First, a support tape is attached to the upper surface of the semiconductor substrate SUB, and the lower surface of the semiconductor substrate SUB is ground to reduce the thickness of the semiconductor substrate SUB to, for example, 80 to 90 micrometers. Then, the ground damage layers are removed by etching the lower surface of SUB with hydrofluoric acid. Thereafter, the n-type field stop region NS and the p-type collector region PC are formed by ion-implantation from the lower surface of the semiconductor-substrate SUB. After these implantation, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, on the lower surface of the semiconductor substrate SUB, under the lower surface of the semiconductor substrate SUB, for example, by a sputtering method, to form a AlSi film, a Ti film, a metal film such as a NiV film and a Au film. The metallic film serves as a collector-electrode CE.

(103) As described above, the semiconductor device 100 according to the first embodiment is manufactured.

(104) The manufacturing method of the first embodiment, similarly to Examination Example 2, it is possible to correspond to the device in which the miniaturization is advanced than Examination Example 1. For example, in order to improve the processing accuracy of the contact hole, the level difference of the upper surface of the interlayer insulating film IL is reduced. For this purpose, a planarization process is performed on the upper surface of the interlayer insulating film IL by CMP method to reduce the thickness of the conductive film PL. In addition, by reducing the thickness of the insulating film IF1 so that the upper surface of the insulating film IF1 is substantially flush with the upper surface of the semiconductor-substrate SUB, the step of the upper surface of the interlayer insulating film IL is reduced.

(105) Even in this case, by forming the insulating layer PL below the conductive film IFL, it is possible to eliminate the problem that the contact hole CH1 penetrates through the conductive film SUB and reaches the semiconductor-substrate OOE. Further, in order to avoid such a defect, since the contact hole CH1 does not require to be formed in a manufacturing process different from the contact hole CH2, there is no need to increase the number of masks and add a manufacturing process, and an increase in manufacturing costs can be suppressed.

(106) In addition, after the contact hole CH1 is formed deeper in the process of FIG. 22 than in the third study, the contact hole CH1 is further deepened by the isotropic etch process of FIG. 23. That is, L1 from the lower surface of the conductive film PL to the bottom portion of the contact hole CH1 is sufficiently long. Accordingly, since the barrier metal film BM is normally formed, the conductive film CF is easily grown sufficiently using the barrier metal film BM as a seed film. In addition, since there is no portion where the barrier metal film BM is very thin, or a portion where the barrier metal film BM is not formed, WF.sub.6 gases react with the conductive film CF, and a part of the conductive film CF is lacking. Therefore, a highly reliable semiconductor device 100 can be manufactured.

(107) Although the present invention has been described based on the above embodiments, the present invention is not limited to the above embodiments, and can be variously modified without departing from the gist thereof.

(108) For example, in the above-described embodiment, IGBT is exemplified as a device formed in the region 2A, but the technique disclosed in the above-described embodiment is not limited to IGBT, and can be applied to a power MOSFET having a vertical trench gate structure.