A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

A display device according to the present disclosure includes: a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate. A gate electrode of the thin film transistor with the top gate structure is provided in a same layer as a wire layer. A method of manufacturing a display device according to the present disclosure, the display device including a thin film transistor with a bottom gate structure and a thin film transistor with a top gate structure on a same substrate, includes: forming a gate electrode of the thin film transistor with the top gate structure in a same layer as a wire layer.

A method for manufacturing a solid state device with a self-forming nanogap includes patterning a first metallic layer (M1) to form a first electrode on a substrate; depositing a self-assembling monolayer, SAM, layer over and around the first electrode; forming a second metallic layer (M2) in contact with the SAM layer and the substrate; and touchlessly removing parts of the second metallic layer (M2) that is formed directly above the SAM layer, to form a second electrode, and a nanogap between the first electrode and the second electrode.

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200 C. to about 600 C. by plasma enhanced chemical vapor deposition (PECVD).

A semiconductor device including a first conductive layer, a second conductive layer over the first conductive layer, a first insulating layer in contact with the first conductive layer and the second conductive layer, a third conductive layer over the first insulating layer, a semiconductor layer in contact with the third conductive layer, the first conductive layer, and the first insulating layer, a second insulating layer over the first insulating layer, the semiconductor layer, and the third conductive layer, and a fourth conductive layer over the second insulating layer is provided. A shortest distance from a top surface of the first conductive layer to a top surface of the second conductive layer is longer than a shortest distance from the top surface of the first conductive layer to a bottom surface of the fourth conductive layer.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

The present application discloses a memory device and a method for fabricating the memory device. The memory device includes a substrate; a landing area positioned on the substrate; a bottom electrode positioned on the landing area, wherein the bottom electrode has a container-shaped profile; a support layer positioned over the substrate and laterally surrounded the bottom electrode; a dielectric structure including a dielectric layer conformally positioned on the bottom electrode and on a top surface of the support layer, and covering top corners of the support layer, and a plurality of dielectric portions conformally positioned on the dielectric layer and covering the top corners of the support layer; and a top electrode structure positioned on the dielectric structure. The dielectric portions are sandwiched by the top electrode structure and the dielectric layer. The top surface of the third support layer is higher than a top surface of the bottom electrode.

Provided is a reflective electrode for a deep ultraviolet light-emitting element that enables a balance of both high light emission output and excellent reliability. A method of producing the reflective electrode for a deep ultraviolet light-emitting element includes: a first step of forming Ni with a thickness of 3 nm to 20 nm as a first metal layer on a p-type contact layer having a superlattice structure; a second step of forming Rh with a thickness of not less than 20 nm and not more than 2 m as a reflective metal on the first metal layer; and a third step of performing heat treatment of the first metal layer and the second metal layer at not lower than 300 C. and not higher than 600 C.

A method of forming a self-aligned contact in a semiconductor device and a semiconductor structure is provided. The method and structure described herein provides for a small cell pitch that enables manufacturing of a semiconductor device with high cell density, and can provide a semiconductor device with improved (reduced) drain-source specific on-resistance R.sub.on,sp.