Disclosed examples include integrated circuits and bipolar transistors with a first region of a first conductivity type in a substrate, a collector region of a second conductivity type disposed in the substrate, and a base region of the first conductivity type extending into the first region. A first emitter region of the second conductivity type extends into the first region and includes a lateral side spaced from and facing the base region. A second emitter region of the second conductivity type extends downward into the first region, abutting the top surface and an upper portion of the first lateral side of the first emitter region to mitigate surface effects and gain degradation caused by hydrogen injection from radiation to provide a radiation hardened bipolar transistor.

A semiconductor device may include a well region disposed in a substrate, an impurity injection region disposed in the well region, an active fin on the well region, a lower insulating layer covering the impurity injection region and the active fin, and a connection pattern provided to penetrate the active fin and connected to the well region. The substrate and the impurity injection region may have a first conductivity type, and the well region may have a second conductivity type different from the first conductivity type. An uppermost portion of the impurity injection region may be in direct contact with the lower insulating layer.

A semiconductor device may include a well region disposed in a substrate, an impurity injection region disposed in the well region, an active fin on the well region, a lower insulating layer covering the impurity injection region and the active fin, and a connection pattern provided to penetrate the active fin and connected to the well region. The substrate and the impurity injection region may have a first conductivity type, and the well region may have a second conductivity type different from the first conductivity type. An uppermost portion of the impurity injection region may be in direct contact with the lower insulating layer.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

A device and methods of forming the same are described. The device includes a substrate and a first bipolar junction transistor (BJT) disposed over the substrate. The first BJT includes a first base region, a first emitter region, and a first collector region. The device further includes a second BJT disposed over the substrate adjacent the first BJT, and the second BJT includes a second base region, a second emitter region, and a second collector region. The device further includes an interconnect structure disposed over the first and second BJTs, and the interconnect structure includes a first conductive line electrically connected to the first emitter region and the second base region and a second conductive line electrically connected to the first collector region and the second collector region.

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

The disclosed technology relates generally to semiconductor devices, and more particularly to semiconductor devices including a metal-oxide-semiconductor (MOS) transistor and are configured for accelerating and monitoring degradation of the gate dielectric of the MOS transistor. In one aspect, a semiconductor device configured with gate dielectric monitoring capability comprises a metal-oxide-semiconductor (MOS) transistor including a source, a drain, a gate, and a backgate region formed in a semiconductor substrate. The semiconductor device additionally comprises a bipolar junction transistor (BJT) including a collector, a base, and an emitter formed in the semiconductor substrate, wherein the backgate region of the MOS transistor serves as the base of the BJT and is independently accessible for activating the BJT. The MOS transistor and the BJT are configured to be concurrently activated by biasing the backgate region independently from the source of the MOS transistor, such that the base of the BJT injects carriers of a first charge type into the backgate region of the MOS transistor, where the first charge type is opposite charge type to channel current carriers.

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

Structures that include bipolar junction transistors and methods of forming such structures. The structure comprises a semiconductor layer, a substrate, and a dielectric layer disposed between the semiconductor layer and the substrate. The structure further comprises a first bipolar junction transistor including a first collector in the substrate, a first emitter, and a first base layer. The first base layer extends through the dielectric layer from the first emitter to the first collector. The structure further comprises a second bipolar junction transistor including a second collector in the substrate, a second emitter, and a second base layer. The second base layer extends through the dielectric layer from the second emitter to the second collector. The second base layer is connected to the first base layer by a section of the semiconductor layer to define a base line.

Disclosed are an ESD protection device to mitigate performance degradation due to operational instability by ensuring protection against ESD events and stress. The ESD protection device includes an N-type buried layer including a first dopant type in a semiconductor substrate, a deep well (DNW) including a first dopant type on the N-type buried layer, a first doped region including a first dopant type on the deep well, a second doped region including a first dopant type and a third doped region including a second dopant type, spaced apart from the first doped region, a base in the first doped region, and a multi-finger structure including emitter fingers in the second doped region and collector fingers in the third doped region, and a base moat comprising a base metal connecting individual ones of the emitter fingers to each other.