A semiconductor device according to an embodiment includes a semiconductor chip having a transistor region and a diode region, and a conductor. The semiconductor chip includes a first electrode, a second electrode, a silicon carbide layer between the first electrode and the second electrode, and a gate electrode. The first electrode includes a first region in the transistor region and a second region in the diode region. A first contact area between the conductor and the first region is larger than a second contact area between the conductor and the second region.

An improved silicon carbide (SiC) planar MOSFET having at least one buried P-shield (BPS) region including one center portion and two side portions for the gate oxide electric field and saturation current reductions is disclosed. Two saturation current pitching (SCP) structures formed in two Junction Field Effect Transistor (JFET) regions sandwiched between the side portions and the center portion of the BPS region limit a saturation current of the device in a forward conduction stage for the short-circuit capability improvement. Moreover, a Junction barrier Schottky diode (JBSD) is integrated with the SiC MOSFET in a location between the two adjacent split gate electrodes for the reverse conduction switching loss reduction.

A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.

A semiconductor device having a connecting region between an active region and an edge region. The semiconductor device including a semiconductor substrate, a first semiconductor layer provided on the semiconductor substrate, a second semiconductor layer provided on the first semiconductor layer, a plurality of first semiconductor regions selectively provided in the second semiconductor layer, a plurality of first and second trenches penetrating through the first semiconductor regions and the second semiconductor layer, a plurality of gate electrodes provided in the first trenches, via a plurality of gate insulating films, respectively, and a plurality of Schottky electrodes respectively provided in the second trenches. The semiconductor substrate, the first and second semiconductor layers, the first semiconductor regions, the first trenches, the gate electrodes and the gate insulating films are provided in the active region. The second trenches and the Schottky electrodes are provided in both the active region and the connecting region.

An SiC semiconductor device includes a first SiC layer, a second SiC layer laminated on the first SiC layer, a first impurity region of a p-type formed in the first SiC layer, a second impurity region of the p-type formed in the second SiC layer, first inversion columns of an n-type that are formed at an interval in the first SiC layer such as to invert a conductivity type of the first impurity region; and second inversion columns of the n-type that are formed at an interval in the second SiC layer such as to invert a conductivity type of the second impurity region.

An SiC semiconductor device includes a first SiC layer of a first conductivity type that has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type that has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type that extends along the first axis channel in the first SiC layer in cross-sectional view and extends in a first extension direction in plan view, and a second region of the second conductivity type that extends along the second axis channel in the second SiC layer in cross-sectional view and extends in a second extension direction intersecting the first extension direction such as to intersect the first region in plan view.

A trench semiconductor structure includes a semiconductor material layer having a first surface and a second surface opposite to the first surface. A first trench structure extends from the first surface toward the second surface, and includes a first electrode, a second electrode above the first electrode, and a first oxide layer surrounding and separating the first electrode and the second electrode. A second trench structure extends from the first surface toward the second surface, and includes a first gate, a third electrode below the first gate, and a second oxide layer surrounding and separating the third electrode and the first gate. A first doped region is provided in the semiconductor material layer, away from the first surface, and between the first trench structure and the second trench structure. A second doped region is provided between the first surface and the first doped region.

An SiC semiconductor device includes a first SiC layer of a first conductivity type which has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type which has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type which extends along the first axis channel in the first SiC layer, and a second region of the second conductivity type which extends along the second axis channel in the second SiC layer and overlaps the first region in the lamination direction.

Provided is a method of manufacturing a silicon carbide semiconductor device capable of ensuring an ohmic contact between a semiconductor layer including silicon carbide and an electrode without any silicide layer provided. The method of manufacturing the silicon carbide semiconductor device, includes: implanting impurity ions into a top surface of a first semiconductor layer including 4H-SiC in a direction inclined at an angle of 30 degrees or greater and less than 90 degrees to a normal line to the top surface of the first semiconductor layer so as to form a second semiconductor layer including 3C-SiC at least at a top surface on the top surface side of the first semiconductor layer; and forming a main electrode on the top surface side of the second semiconductor layer.

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region including a first portion. The second semiconductor region is provided on the first portion. The gate electrode faces the first portion via a gate insulating layer. The second electrode includes platinum, cobalt, or nickel. The second electrode includes a first electrode portion and a second electrode portion. The first electrode portion is arranged with the first portion and the second semiconductor region in the second direction. The first portion is positioned between the first electrode portion and the gate electrode. The second electrode portion is provided on the gate electrode via an insulating layer. The second semiconductor region is positioned between the first electrode portion and the second electrode portion.