A semiconductor device includes a semiconductor layer having a main surface in which a gate trench is formed, a gate insulating layer formed along an inner wall of the gate trench, a gate electrode layer constituted of a polysilicon and embedded in the gate trench across the gate insulating layer, and a low resistance electrode layer including a conductive material having a sheet resistance less than a sheet resistance of the gate electrode layer and covering the gate electrode layer.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A semiconductor device of embodiments includes an element region, a termination region, and an intermediate region between the element region and the termination region. The element region includes: a silicon carbide layer having a first conductive type silicon carbide region and a second conductive type of silicon carbide regions; and a gate electrode. The intermediate region includes a silicon carbide layer having a second conductive type silicon carbide region outside the second conductive type silicon carbide regions. The width of the second conductive type silicon carbide region in the intermediate region is equal to or more than 0.5 times and equal to or less than 3 times the width of the second conductive type silicon carbide region in the element region.

Disclosed is a cellular structure of a silicon carbide MOSFET device, and a silicon carbide MOSFET device. The cellular structure comprises: second conductive well regions located on two sides of the cellular structure and arranged within the surface of a drift layer, first conductive source regions located within the surfaces of the well regions, and a gate structure located at the center of the cellular structure and in contact with the source regions, the well regions, and the drift layer. The cellular structure further comprises a source metal layer located above the source regions and forming ohmic contact with the source regions; on two sides of the cellular structure, side trenches are formed downwardly on regions of the drift layer that are not covered by the well regions; Schottky metal layers forming Schottky contact with the drift layer below the side trenches are arranged in the side trenches.

According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductive type between a first electrode and a second electrode. A third electrode extends from the first electrode toward the second electrode. A fourth electrode faces the third electrode. A second semiconductor region of second conductive type which is between the third electrode and the fourth electrode and contacts the third electrode. An insulation layer is in contact with the fourth electrode and faces the third electrode. A third semiconductor region of first conductive type is between the second electrode and the second semiconductor region. The third semiconductor region has a higher impurity concentration than the first semiconductor region.

There is provided a diode including an anode electrode provided on a side of a front surface of a semiconductor substrate, an interlayer dielectric film disposed between the semiconductor substrate and the anode electrode, a first anode region of a first conductivity type provided on the front surface of the semiconductor substrate, a second anode region of a second conductivity type, which is different from the first conductivity type, provided on the front surface of the semiconductor substrate, a first contact hole provided in the interlayer dielectric film, causing the anode electrode to be in Schottky contact with the first anode region, and a second contact hole provided in the interlayer dielectric film and different from the first contact hole, causing the anode electrode to be in ohmic contact with the second anode region.

A power semiconductor device includes a semiconductor structure having a first side, a second side, and a drift region of a first conductivity type therebetween, and implanted regions of a second conductivity type in the semiconductor structure adjacent the first side of the semiconductor structure. The implanted regions include first portions of a first material and second portions of a second material, with the second portions positioned between the first portions and the second side. The second material has an atomic weight that is lighter than that of the first material. Related fabrication methods are also discussed.

An integrated circuit comprising a SiC MOSFET and a SiC super barrier rectifier (SBR) disposed in one unit cell having an asymmetric trench gate electrode structure formed in a stripe gate trench is disclosed. A first channel region of the SiC MOSFET is formed along a first trench sidewall of the gate trench while a second channel region of the SiC SBR is formed along a first portion of a second trench sidewall opposite to the first trench sidewall of the gate trench. A source metal connects with a source region, body regions, and the gate electrode of the SiC SBR directly, and connects with a P-shield (PS) region below the gate trench through a grounded P (GP) region along a second portion of the second gate trench sidewall.

A semiconductor device includes a semiconductor member, a gate electrode, and a source electrode. The semiconductor member has a groove part and a recess. At least a part of the source electrode is disposed inside the recess. The semiconductor member has a drift region and a mesa region. The drift region and the mesa region have first conductivity type impurities. The drift region is positioned on a first side relative to a bottom of the groove part. The mesa region is positioned between a pair of the groove parts in a second direction. The mesa region has a Schottky junction that forms a Schottky junction with the source electrode. The Schottky junction is positioned on a second side relative to an end on the first side of the source electrode and on the second side relative to an end on the first side of the gate electrode.

A semiconductor device of embodiments includes an element region and a termination region surrounding the element region. The termination region includes: a silicon carbide layer having a silicon carbide region of a first conductive type, a first silicon carbide region of the second conductive type on the silicon carbide region, and a second silicon carbide region of the second conductive type on the silicon carbide region spaced apart from the first silicon carbide region and surrounding the first silicon carbide region. In the termination region, one contact portion of a wiring layer is connected to the first silicon carbide region, and another contact portion of the wiring layer is connected to the second silicon carbide region. A second conductive type impurity concentration of the first silicon carbide region below the one contact portion is lower than that of the second silicon carbide region below the another contact portion.